Simplified Run-Time Program Translation for Emulating Complex Processor Pipelines

• US 20090083513A1
• Filed: 09/21/2008
• Published: 03/26/2009
• Est. Priority Date: 09/20/2007
• Status: Active Grant

• Current Assignee: Sony Interactive Entertainment Inc. (Sony Group Corp.)
• Original Assignee: Sony Interactive Entertainment Inc. (Sony Group Corp.)
• Inventors: Miura, Victor O.S., Sargaison, Stewart
• Granted Patent: US 9,483,405 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures

Abstract

Simplification of run-time program translation for emulating complex processor pipelines is disclosed. Problem of dynamic pipeline states are moved into a cache lookup process leaving a code translation process to deal only with static pipeline states. With dynamic pipeline states removed from the translation process, translation becomes more simple and efficient like that of a non-pipelined processor.

Claims

1. A method for program translation in a processor pipeline, the method comprising:

determining a current target address and pipeline signature;

looking up a corresponding target address and pipeline signature entry; and

producing a translation for the current target address and pipeline signature when there is no corresponding target address and pipeline signature entry.

2. The method of claim 1, where the target address and pipeline signature entry are looked up in a hash table.

3. The method of claim 1, wherein the corresponding target address and pipeline signature are static values.

4. The method of claim 1, wherein the translation is only valid for a single address and pipeline signature pair.

5. The method of claim 1, further comprising saving the translation in a translation cache.

6. The method of claim 5, further comprising executing the translation.

7. A method for program translation in a processor pipeline, the method comprising:

determining a current target address and pipeline signature;

looking up a corresponding target address and pipeline signature entry; and

executing a translation corresponding to the current target address and pipeline signature when there is a corresponding target address and pipeline signature entry.

8. The method of claim 7, where the target address and pipeline signature entry are looked up in a hash table.

9. The method of claim 7, wherein the corresponding target address and pipeline signature are static values.

10. The method of claim 7, wherein the translation is only valid for a single address and pipeline signature pair.

11. A processor pipeline translation method, comprising:

decoding an address pipeline signature pair;

checking for a stall;

calling a code generation function for lower and upper instructions; and

updating the address pipeline signature pair.

12. The method of claim 11, wherein the code generation function maps the required input registers.

13. The method of claim 12, wherein the mapped input registers are maintained in a temporary register.

14. The method of claim 13, further comprising creating a record for a write back operation.

15. The method of claim 12, further comprising writing back the mapped input registers to a register file.

16. The method of claim 11, wherein the stall is checked with respect to VF and VI stalls.

17. The method of claim 16, wherein the stall is checked using current VFRD, VIRU, and VIS[] information.