SYSTEM FOR AND METHOD OF INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT

• US 20090083690A1
• Filed: 09/24/2007
• Published: 03/26/2009
• Est. Priority Date: 09/24/2007
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: McMahon, Robert, Habib, Nazmul, Perry, Troy
• Application Number:
  US11/859,965
• Publication Number:
  US 20090083690A1
• Time in Patent Office: Days
• US Class Current: 716/104
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A system and method for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of devices contained in the IC. The test structures are built from a device under test (DUT) library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design to be manufactured.

Claims

1. A method comprising:

identifying at least one device under test (DUT) which matches at least one device in an integrated circuit (IC) design;

generating a first test structure comprising a control structure coupled to the at least one DUT; and

modifying the IC design to include the first test structure.

2. The method of claim 1 further comprising:

generating a list of a plurality of DUTs which match at least one of a plurality of devices in the integrated circuit design.

3. The method of claim 2 further comprising:

generating a prioritized list from the list of the plurality of DUTs using at least one prioritization algorithm and at least one of a plurality of customer directives, a plurality of historical data, or a plurality of internal rules.

4. The method of claim 2 further comprising

storing in a database at least one of the plurality of DUTs which is in the list but which is not in the first test structure.

5. The method of claim 3, further comprising:

using at least one of a plurality of placement algorithms to place the at least one DUT from the prioritized list into the design.

6. The method of claim 1 further comprising:

determining whether area is available in the integrated circuit for the first test structure.

7. The method of claim 1 further comprising:

determining whether an element is available in the integrated circuit for coupling to the first test structure.

8. The method of claim 1 further comprising:

assigning the control structure to an element in the IC design.

9. A system comprising:

an IC design comprising at least one device and at least one element;

a library comprising at least one device under test (DUT), wherein the at least one DUT matches the at least one device; and

a modified IC design comprising at least one control structure, the control structure coupled to the at least one DUT and the at least one element.

10. The system of claim 9 further comprising:

a first list comprising a plurality of matching DUTs.

11. The system of claim 10 further comprising:

a second list generated from the first list and a first database comprising priority specifications;

the second list comprising a plurality of prioritized matching DUTs.

12. The system of claim 11, wherein the first database comprises at least one of a plurality of customer directives, a plurality of historical data, or a plurality of internal rules.

13. The system of claim 11 further comprising:

at least one placement algorithm for placing at least one of the plurality of prioritized matching DUTs into the IC design.

14. The system of claim 11 further comprising:

a third list comprising at least a portion of the plurality of prioritized matching DUTs corresponding to a plurality of elements,

the third list is generated from the second list and a second database comprising the plurality of elements, the elements corresponding to the IC design.

15. The system of claim 14 further comprising a third database, the third database comprising at least a second portion prioritized matching DUTs which are not in the third list.

16. A computer readable program product embodied in a computer readable medium, the program product causing a computer to:

identify a first device under test (DUT) the first DUT matching at least one device in an integrated circuit (IC) design; and

modify the IC design to include the first DUT coupled to a control structure and at least one element in the IC design.

17. The computer readable program product of claim 16 further causing a computer to:

generate a list of a plurality of DUTs which match at least one of a plurality of devices in the IC design.

18. The computer readable program product of claim 17 further causing a computer to:

generate a prioritized list from the list of the plurality of DUTs using at least one prioritization algorithm and at least one of a plurality of customer directives, a plurality of historical data, or a plurality of internal rules.

19. The computer readable program product of claim 17 further causing a computer to:

store in a database at least one of the plurality of DUTs which is in the list but which is not in the integrated circuit design.

20. The computer readable program product of claim 18 further causing a computer to:

use at least one of a plurality of placement algorithms to place the at least one DUT from the prioritized list into the design.

21. The computer readable program product of claim 16 further causing a computer to:

determine whether area is available in the integrated circuit for the first test structure.

22. The computer readable program product of claim 16 further causing a computer to:

determine whether an element is available in the integrated circuit for coupling to the first test structure.

23. The computer readable program product of claim 22 further causing a computer to:

assign the first test structure to the element in the design; and

store the assignment in an assignment list.

24. The computer readable program product of claim 16 further causing a computer to:

compile the modified design; and

perform a plurality of design checking algorithms.