Integrated Circuit and Methods of Manufacturing the Same

• US 20090085084A1
• Filed: 09/28/2007
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Mierau, Uta, Tegen, Stefan, Muemmler, Klaus, Baars, Peter
• Granted Patent: US 7,851,356 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A method of manufacturing an integrated circuit includes forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region. The method also includes forming wiring lines within a peripheral region of the substrate. Forming the landing pads and forming the wiring lines includes a common lithographic process being effective in both the array and peripheral regions. The wiring lines and the landing pads of the integrated circuit are self-aligned.

Claims

1. A method of manufacturing an integrated circuit, the method comprising:

forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region; and

forming wiring lines within a peripheral region of the substrate;

wherein forming the landing pads and forming the wiring lines comprises a common lithographic process being effective both in the array and peripheral regions.

2. The method of claim 1, further comprising:

forming contact plugs in the array region before forming the landing pads, lower surfaces of the individual ones of the contact plugs being in contact with individual ones of the portions of the devices and upper surfaces of the individual ones of the contact plugs being in contact with individual ones of the landing pads.

3. The method of claim 1, wherein forming the landing pads and forming the wiring lines further comprises:

patterning a layer of a conductive material disposed in the peripheral region and in the array region such that the conductive material is electrically coupled to the portions of the devices.

4. The method of claim 1, further comprising:

providing a conductive layer above the peripheral region and the array region before carrying out the common lithographic process, the conductive layer being electrically coupled to the portions of the devices;

providing a masking layer above the conductive layer and patterning the masking layer by carrying out the common lithographic process to form landing pad structures within the masking layer in the array region and wiring line structures within the masking layer in the peripheral region; and

patterning the conductive layer using the patterned masking layer as an etching mask.

5. The method of claim 4, further comprising:

forming contact portions comprising a semiconductor material, the contact portions being exposed at a top surface of the array region and electrically coupling the conductive layer to the portions of the devices; and

forming a metal-semiconductor compound before providing the conductive layer.

6. The method of claim 1, further comprising:

providing a masking layer above the peripheral region and the array region before carrying out the common lithographic process;

patterning the masking layer by carrying out the common lithographic process, thereby forming structures in the masking layer, the structures being holes having the shape of the landing pads in the array region and being trenches having the shape of the wiring lines in the peripheral region; and

at least partially filling the structures in the masking layer with a conductive material.

7. The method of claim 6, further comprising:

forming contact portions in the array region, the contact portions being electrically coupled to the portions of the devices;

wherein the structures in the array region extend to an upper surface of the contact portions.

8. The method of claim 7, further comprising:

forming a metal-semiconductor compound in the structures above the contact portions before filling the structures with the conductive material;

wherein the contact portions comprise a semiconductor material.

9. The method of claim 1, wherein the common lithographic process comprises:

a first lithographic exposure process using a first mask comprising first line structures in an array portion corresponding to the array region and wiring line structures in an peripheral portion corresponding to the peripheral region; and

a second lithographic exposure process using a second mask with second line structures in an array portion corresponding to the array region and with a block structure in a peripheral portion corresponding to the peripheral region, the second line structures intersecting the first line structures.

10. The method of claim 9, wherein the first and second lithographic exposure processes are effective on one resist layer system.

11. The method of claim 9, wherein the first lithographic exposure process is effective on a first resist layer system and the second lithographic process is effective on a second resist layer system.

12. The method of claim 1, wherein the devices formed in the array region are access transistors of memory cells and the portions of the devices are source/drain regions of the transistors, the method further comprising:

forming first and second conductive lines in the array region, individual ones of the access transistors being configured to be addressed by at least one first and one second conductive line; and

forming storage capacitors above the access transistors in the array region, individual ones of the storage capacitors being electrically coupled to individual ones of the landing pads.

13. An integrated circuit comprising:

a plurality of devices disposed in an array region of a substrate, individual ones of the devices being formed at least partially within the substrate;

a plurality of contact structures, individual ones of the contact structures comprising a landing pad being electrically coupled to a portion of one of the devices; and

a wiring layer disposed in a peripheral region of the substrate, the wiring layer comprising wiring lines being self-aligned to the landing pads.

14. The integrated circuit of claim 13, wherein individual ones of the contact structures comprise:

a contact plug being in contact with the portion of one of the devices, the landing pad being disposed above and in contact with the contact plug.

15. The integrated circuit of claim 14, wherein a width of the contact plugs is smaller than 1.5×

F, the width being measured parallel to a surface of the substrate and F denoting the minimum lithographic feature size.

16. The integrated circuit of claim 13, wherein individual ones of the contact structures comprise:

a contact portion being in contact with one landing pad and electrically coupling the one landing pad to the portion of the device, a width of the contact portion being smaller than 1.5×

F, the width being measured parallel to a surface of the substrate and F denoting the minimum lithographic feature size.

17. The integrated circuit of claim 13, wherein a width of the landing pads is smaller than 2×

F, the width being measured parallel to a surface of the substrate and F denoting the minimum lithographic feature size.

18. The integrated circuit of claim 13, further comprising:

conductive lines disposed in the array region, wherein the landing pads are disposed above the conductive lines.

19. The integrated circuit of claim 13, wherein the landing pads and the wiring lines comprise a common conductive material.

20. The integrated circuit of claim 13, wherein the individual ones of the contact structures comprise:

a contact portion in contact with and electrically coupling the landing pad to the portion of the device, the contact portion comprising a first conductive material and the landing pad comprising a second conductive material that is different from the first conductive material.

21. The integrated circuit of claim 13, wherein the individual ones of the contact structures comprise:

a contact portion electrically coupling the landing pad to the portion of the device, the contact portion comprising a semiconductor material; and

a metal-semiconductor compound arranged between the contact portions and the landing pads.

22. The integrated circuit of claim 13, wherein the individual ones of the contact structures comprise:

a contact portion in contact with and electrically coupling the landing pad to the portion of the device, the contact portion comprising one of;

a metal, a metal nitride or a metal carbide.

23. The integrated circuit of claim 13, further comprising:

an insulating material arranged above a surface of the substrate in the peripheral region; and

an additional layer arranged between the insulating layer and the wiring layer in the peripheral region;

wherein the individual ones of the contact structures further comprise a contact portion in contact with and electrically coupling the landing pad to the portion of the device, an upper surface of the insulating layer being at the same height as an upper surface of the contact portion.

24. The integrated circuit of claim 13, wherein the devices formed in the array region are access transistors of memory cells and the portions of the devices are source/drain regions of the transistors, the integrated circuit further comprising:

a plurality of first and second conductive lines in the array region, individual ones of the access transistors being configured to be addressed by at least one first and one second conductive line; and

a plurality of storage capacitors arranged above the access transistors in the array region, individual ones of the storage capacitors being electrically coupled to individual ones of the landing pads.

25. An integrated circuit comprising:

a plurality of devices disposed in an array region of a substrate, individual ones of the devices being formed at least partially within the substrate;

a plurality of contact structures, individual ones of the contact structures comprising a landing pad electrically coupled to a portion of one of the devices; and

a wiring layer comprising wiring lines, the wiring layer being disposed in a peripheral region of the substrate and being arranged at the same wiring level as the landing pads.

26. The integrated circuit of claim 25, wherein an upper surface of the wiring layer in the peripheral region and an upper surface of the landing pads in the array region are arranged at the same height above a surface of the substrate.

27. The integrated circuit of claim 25, wherein a lower surface of the wiring layer in the peripheral region and a lower surface of the landing pads in the array region are arranged at the same height above a surface of the substrate.

28. The integrated circuit of claim 25, wherein the landing pads and the wiring lines comprise a common conductive material.

29. The integrated circuit of claim 25, further comprising:

an insulating material arranged above a surface of the substrate in the peripheral region; and

an additional layer arranged between the insulating layer and the wiring layer in the peripheral region;

wherein the individual ones of the contact structures further comprise a contact portion in contact with and electrically coupling the landing pad to the portion of the device, an upper surface of the insulating layer is at the same height as an upper surface of the contact portions in the array region.

30. The integrated circuit of claim 25, wherein the devices formed in the array region are access transistors of memory cells and the portions of the devices are source/drain regions of the transistors, the integrated circuit further comprising:

a plurality of first and second conductive lines in the array region, individual ones of the access transistors being configured to be addressed by at least one first and one second conductive line; and

a plurality of storage capacitors arranged above the access transistors in the array region, individual ones of the storage capacitors being electrically coupled to individual ones of the landing pads.

31. An electronic system including:

an integrated circuit comprising;

a plurality of devices in an array region of a substrate, individual ones of the devices being formed at least partially within the substrate;

a plurality of contact structures, individual ones of the contact structures comprising a landing pad electrically coupled to a portion of one of the devices; and

a peripheral region of the substrate comprising a wiring layer comprising wiring lines, the wiring lines being self-aligned to the landing pads.