TWO-BIT FLASH MEMORY

• US 20090085089A1
• Filed: 04/08/2008
• Published: 04/02/2009
• Est. Priority Date: 10/02/2007
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Chang, Yi-Feng, Chang, Ming-Cheng, Wang, Jer-Chyi, Liao, Wei-Ming
• Granted Patent: US 7,956,403 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation

Abstract

A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.

Claims

1. A flash memory comprising:

a substrate having a protrusion extending from a top face of the substrate;

a control gate, formed on the protrusion of the substrate and extendedly covering two opposite sidewalls of the protrusion;

two floating gates, formed on top of the protrusion and being on two opposite sides of the control gate respectively; and

a dielectric layer, sandwiched by the control gate and each of the two floating gates.

2. The flash memory as claimed in claim 1, further comprising a plurality of isolation structures formed on two opposite sides of the protrusion to sandwich therebetween a source and a drain respectively formed on two opposite sides of the protrusion and each being adjacent to one of the two floating gates.

3. The flash memory as claimed in claim 2, wherein a top surface of the isolation structures is coplanar with that of the two floating gates.

4. The flash memory as claimed in claim 2, wherein the top surface of the isolation structures has a height lower than that of a bottom surface of the two floating gates.

5. The flash memory as claimed in claim 1, wherein the dielectric layer is further sandwiched by the control gate and the protrusion.

6. The flash memory as claimed in claim 5, further comprising an insulating layer sandwiched by the two floating gates and the protrusion.

7. The flash memory as claimed in claim 1, wherein the dielectric layer comprises an oxide-nitride-oxide structure.

8. A flash memory comprising:

a substrate, having a channel region;

a source and a drain respectively formed on a first set of two opposite sides of the channel region in the substrate;

a control gate, formed on top of the channel region to cover a portion of a second set of two opposite sides of the channel region;

two floating gates, respectively formed on two opposite sidewalls of the control gate and on top of the channel region;

an insulating layer, sandwiched by each of the two floating gates and the channel region; and

a dielectric layer, sandwiched by the control gate and the floating gates.

9. The flash memory as claimed in claim 8, wherein the first set of two opposite sides are orthogonal to the second set of two opposite sides of the channel region.

10. The flash memory as claimed in claim 8, further comprising a plurality of isolation structures formed on the second set of two opposite sides of the channel region to sandwich therebetween a source and a drain respectively formed on the first set of two opposite sides of the channel region and each of the source and the drain being adjacent to one of the two floating gates.

11. The flash memory as claimed in claim 10, wherein a top surface of the isolation structures is coplanar with that of the two floating gates.

12. The flash memory as claimed in claim 10, wherein a top surface of the isolation structures has a height lower than that of a bottom surface of the two floating gates.

13. The flash memory as claimed in claim 8, wherein the dielectric layer is further sandwiched by the control gate and the channel region.

14. The flash memory as claimed in claim 13, wherein the dielectric layer comprises an oxide-nitride-oxide structure.