Trench MOSFET with thick bottom oxide tub

• US 20090085107A1
• Filed: 09/28/2007
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Abandoned Application

• Current Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Original Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Inventors: Hshieh, Fwu-Iuan
• Application Number:
  US11/904,840
• Publication Number:
  US 20090085107A1
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor power device includes a plurality of trenched gates. The trenched gates include a thin dielectric layer padded sidewalls of the trenched gate and a tub-shaped thick dielectric layer below a bottom of the trenched gates having a width narrower than the trenched gate. In an exemplary embodiment, the tub-shaped thick dielectric layer below a bottom of the trenched gates further includes a local deposition of silicon oxide (LOCOS) filling in a tub-shaped trench having a narrower width than the trenched gate. In another exemplary embodiment, the tub-shaped thick dielectric layer below a bottom of the trenched gates further comprising a high density plasma (HDP) chemical vapor deposition (CVD) silicon oxide filled in a tub-shaped trench having a narrower width than the trenched gate.

Claims

1. A semiconductor power device comprising:

a plurality of trenched gates comprising a thin dielectric layer padded sidewalls of said trenched gate and a tub-shaped thick dielectric layer below a bottom of said trenched gates having a width narrower than said trenched gate.

2. The semiconductor power device of claim 1 wherein:

said tub-shaped thick dielectric layer below a bottom of said trenched gates further comprising a local oxidation of silicon oxide (LOCOS) filling in a tub-shaped trench having a narrower width than said trenched gate.

3. The semiconductor power device of claim 1 wherein:

said tub-shaped thick dielectric layer below a bottom of said trenched gates further comprising a high density processing (HDP) vapor deposition (CVD) silicon oxide filling in a tub-shaped trench having a narrower width than said trenched gate.

4. The semiconductor power device of claim 1 further comprising:

a dopant region surrounding said tub-shaped thick dielectric layer having a higher dopant concentration than an epitaxial layer in a semiconductor substrate for further reduction of on-resistance.

5. The semiconductor power device of claim 1 further comprising:

a trenched metal oxide semiconductor field effect transistor (MOSFET) device.

6. The semiconductor power device of claim 1 further comprising:

a N-channel trenched metal oxide semiconductor field effect transistor (MOSFET) device.

7. The semiconductor power device of claim 1 further comprising:

a N-channel trenched metal oxide semiconductor field effect transistor (MOSFET) device; and

a N dopant region surrounding said tub-shaped thick dielectric layer having a higher dopant concentration than an N-type epitaxial layer in a semiconductor substrate for further reducing an on-resistance.

8. The semiconductor power device of claim 1 further comprising:

a P-channel trenched metal oxide semiconductor field effect transistor (MOSFET) device.

9. The semiconductor power device of claim 1 further comprising:

a P-channel trenched metal oxide semiconductor field effect transistor (MOSFET) device; and

a P-dopant region surrounding said tub-shaped thick dielectric layer having a higher dopant concentration than an P-type epitaxial layer in a semiconductor substrate for forming and supporting said semiconductor power device therein.

10. The semiconductor power device wherein:

said plurality of trenched gates having a width of approximately 0.3 um to 1.0 um and said tub shaped thick oxide layer having a width of approximately 0.2 um to 0.8 um

11. A method of manufacturing a semiconductor power device comprising:

opening plurality of trenches and covering sidewalls and a bottom surface of said trenches with padded layers; and

applying an isotropic etch for vertically etching said trenches into a tub-shaped opening below said bottom surface of said trenches with a width of said tub-shaped opening smaller than a width said trenches covering by said padded layers.

12. The method of claim 11 further comprising:

filling said tub-shaped opening below said trenches with a thick dielectric layer.

13. The method of claim 11 further comprising:

filling said tub-shaped opening below said trenches with a thick local oxidation of silicon oxide (LOCOS) layer.

14. The method of claim 11 further comprising:

filling said tub-shaped opening below said trenches with a thick high density plasma (HDP) oxide layer.

15. The method of claim 11 wherein:

said step of covering said sidewalls of said trenches with padded layers further comprising covering sidewalls of said trenches with a nitride layer having a lower rate of oxidation while a thick oxide layer is formed in said tub-shaped opening below said trenches with a higher oxidation rate.

16. The method of claim 11 further comprising:

filling said tub-shaped opening below said trenches with a thick local oxidation of silicon oxide (LOCOS) layer with a two-dimensional oxidation in two directions (2D) along a bottom surface and sidewalls of said tub-shaped opening below said trenches.

17. The method of claim 11 further comprising:

filling said tub-shaped opening below said trenches with a thick high density plasma (HDP) oxide layer.

18. The method of claim 11 further comprising:

implanting a dopant region surrounding said tub-shaped opening below said trenches for further reducing an on resistance of said semiconductor power device.