Semiconductor device and method of manufacturing semiconductor device

• US 20090085109A1
• Filed: 09/26/2008
• Published: 04/02/2009
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Izumi, Naoki
• Granted Patent: US 8,426,912 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer; a trench dug from the surface of the semiconductor layer to penetrate the body region; a source region of a first conductivity type formed on a side portion of the trench in a surface layer portion of the body region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode embedded in the trench through the gate insulating film and so formed that the surface thereof is lower by one stage than the surface of the source region; and a peripheral wall film formed on a peripheral edge portion of the surface of the gate electrode to be opposed to an upper end portion of the side surface of the trench.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type;

a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer;

a trench dug from the surface of the semiconductor layer to penetrate the body region;

a source region of a first conductivity type formed on a side portion of the trench in a surface layer portion of the body region;

a gate insulating film formed on the bottom surface and the side surface of the trench;

a gate electrode embedded in the trench through the gate insulating film and so formed that the surface thereof is lower by one stage than the surface of the source region; and

a peripheral wall film formed on a peripheral edge portion of the surface of the gate electrode to be opposed to an upper end portion of the side surface of the trench.

2. The semiconductor device according to claim 1, further comprising an element isolation portion formed on the surface of the semiconductor layer for isolating a first element forming region and a second element forming region from each other, wherein

the body region is formed in the first element forming region, and

a planar gate MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) is formed in the second element forming region.

3. The semiconductor device according to claim 2, wherein

the planar gate MOSFET comprises:

a planar gate electrode formed on the surface of the semiconductor layer in the second element forming region; and

a sidewall surrounding the planar gate electrode to cover the side surface of the planar gate electrode.

4. The semiconductor device according to claim 2, further comprising:

a deep well region of a second conductivity type formed in the surface layer portion of the semiconductor layer in the second element forming region;

a first well region of a first conductivity type formed in a surface layer portion of the deep well region; and

a second well region of a second conductivity type formed in the surface layer portion of the deep well region isolatedly from the first well region.

5. A method of manufacturing a semiconductor device having a trench gate VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field-Effect Transistor) and a planar gate MOSFET, comprising the steps of:

forming a trench dug from the surface of a semiconductor layer of a first conductivity type in a first element forming region on which the trench gate VDMOSFET is formed;

forming a trench gate electrode having a surface lower by one stage than the surface of the semiconductor layer in the trench;

forming a planar gate electrode on the surface of the semiconductor layer in a second element forming region on which the planar gate MOSFET is formed;

forming a deposition layer of an insulating material on the surface of the semiconductor layer, the trench gate electrode and the planar gate electrode after the formation of the trench gate electrode and the planar gate electrode; and

forming a peripheral wall film and a sidewall by partially leaving the deposition layer on a peripheral edge portion of the surface of the trench gate electrode and a side portion of the planar gate electrode respectively by etching back the deposition layer.

6. The method of manufacturing a semiconductor device according to claim 5, further comprising the steps of:

forming a body region recess for forming a body region of the trench gate VDMOSFET on the semiconductor layer in the first element forming region; and

embedding a semiconductor material of a second conductivity type in the body region recess by epitaxy or CVD (Chemical Vapor Deposition).

7. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming a well region recess for forming a well region of the planar gate MOSFET on the semiconductor layer in the second element forming region, wherein

the semiconductor material is embedded in the well region recess in parallel with the embedding of the semiconductor material in the body region recess.

8. A method of manufacturing a semiconductor device having a VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field-Effect Transistor) and a planar gate MOSFET, comprising the steps of:

forming a semiconductor layer of a first conductivity type by epitaxy;

forming a body region recess for forming a body region of the VDMOSFET on the semiconductor layer; and

embedding a semiconductor material of a second conductivity type in the body region recess by epitaxy or CVD (Chemical Vapor Deposition).

9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of forming a well region recess for forming a well region of the planar gate MOSFET on the semiconductor layer, wherein

the semiconductor material is embedded in the well region recess in parallel with the embedding of the semiconductor material in the body region recess.

10. A method of manufacturing a semiconductor device having a VDMOSFET and a planar gate MOSFET, comprising the steps of:

forming a first semiconductor layer of a first conductivity type by epitaxy;

forming a second semiconductor layer of a second conductivity type on the first semiconductor layer by epitaxy or CVD; and

forming a body region of a second conductivity type of the VDMOSFET and a well region of a second conductivity type of the planar gate MOSFET isolatedly from each other by selectively implanting a first conductivity type impurity into the second semiconductor layer.

11. A semiconductor device having a VDMOSFET and a planar gate MOSFET, comprising:

a semiconductor layer of a first conductivity type;

a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer in a first element forming region on which the VDMOSFET is formed; and

a well region of a second conductivity type formed in the surface layer portion of the semiconductor layer in a second element forming region on which the planar gate MOSFET is formed, wherein

the body region and the well region have the same impurity concentration profiles, with generally uniform impurity concentrations in the depth directions respectively.