POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT

• US 20090085122A1
• Filed: 10/01/2007
• Published: 04/02/2009
• Est. Priority Date: 10/01/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Teh, Young Way, Zhang, Fan, Ho, Vincent, Sheng, Haifeng, Siew, Yong Kong, Lin, Wenhe, Zhang, Bei Chao, Tan, Juan Boon
• Granted Patent: US 7,993,997 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Claims

1. A method of inducing stress in a semiconductor device substrate comprising:

applying an ion implantation to a target gate region before a source/drain annealing process;

source/drain annealing said target gate region wherein a gate formed in said target gate region is expanded due to said ion implantation; and

completing the fabrication of a semiconductor device on said semiconductor substrate, whereby stress caused by said expansion of said gate is transferred to said semiconductor substrate.

2. The method of claim 1 wherein said applying comprises applying ion implantation to a polysilicon film.

3. The method of claim 1 wherein said applying comprises applying ion implantation to a polysilicon gate.

4. The method of claim 3 wherein said applying comprises applying ion implantation to a polysilicon gate having sidewall spacers.

5. The method of claim 1 wherein said applying comprises applying a germanium ion implantation.

6. The method of claim 1 wherein said annealing comprises increasing the width of said gate.

7. The method of claim 1 wherein said semiconductor device is an NFET device and said annealing comprises increasing the width of the upper portion of said gate.

8. The method of claim 7 further comprising applying downward forces on said semiconductor device substrate adjacent to said gate.

9. The method of claim 1 wherein said semiconductor device is a PFET device and said annealing comprises increasing the width of the lower portion of said gate.

10. The method of claim 9 further comprising applying upward forces on said semiconductor device substrate adjacent to said gate.

11. A method of processing a semiconductor device comprising:

forming a polysilicon film on a semiconductor substrate including target and non-target regions;

forming a photo resist layer over said non-target region of said semiconductor substrate;

forming a mask over said non-target region of said semiconductor substrate;

ion implanting said polysilicon film over said target region of said semiconductor substrate, said second predetermined region being different from, and adjacent to, said first predetermined region; and

annealing a gate formed on said implanted polysilicon film.

12. The method of claim 11 further comprising expanding the dimensions of said gate during said annealing.

13. The method of claim 12 further comprising forming sidewall spacers adjacent to said gate.

14. The method of claim 13 further comprising transferring forces caused by said expanding of the dimensions of said gate to said sidewall spacers.

15. The method of claim 14 further comprising transferring said forces through said sidewall spacers to said semiconductor substrate below said sidewall spacers.

16. The method of claim 11 further comprising:

repeating said steps of forming a photo resist layer, forming a mask and ion implanting on different regions of said semiconductor substrate and under different ion implantation conditions, said conditions including at least one of;

ion implantation dosages and ion implantation energies.

17. The method of claim 16 wherein said different regions of said semiconductor substrate having ion implanting under different conditions include regions of semiconductor devices including at least two of the following:

low voltage threshold devices, medium voltage threshold devices and high voltage threshold devices.

18. A transistor comprising:

a semiconductor substrate;

a source in said semiconductor substrate;

a drain in said semiconductor substrate; and

a gate on said semiconductor substrate, said gate having bulging sidewalls.

19. The transistor of claim 18 wherein said bulging sidewalls are disposed near the top of said gate.

20. The transistor of claim 20 wherein said bulging sidewalls are disposed near the bottom of said gate.