SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20090085131A1
• Filed: 09/25/2008
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: MATSUBARA, Yoshihisa
• Application Number:
  US12/237,433
• Publication Number:
  US 20090085131A1
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The semiconductor device includes: a semiconductor substrate; a diffusion layer provided in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate; a gate electrode provided on the gate insulation film; and a Ni silicide layer selectively provided on the diffusion layer, and a metal cap film having Co as a main component is selectively provided on the Ni silicide layer.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a diffusion layer provided in said semiconductor substrate;

a gate insulation film provided over said semiconductor substrate;

a gate electrode provided over said gate insulation film; and

a metallic silicide layer having Ni as a main component which is selectively provided over said diffusion layer,

wherein a metal cap film having Co as a main component, is selectively provided over said silicide layer.

2. The semiconductor device according to claim 1,

wherein said metallic silicide layer further includes Pt.

3. The semiconductor device according to claim 1,

wherein said silicide layer is divided into a plurality of regions by said diffusion layer, and, at the same time, said metal cap film is provided even over the diffusion layer by which said silicide layer is divided into said plurality of regions.

4. The semiconductor device according to claim 1,

wherein said silicide layer is divided into a plurality of regions by said diffusion layer, and at the same time,

said silicide layers provided in said plurality of regions are connected through said metal cap film.

5. The semiconductor device according to claim 1, further comprising:

a side wall insulation film provided over the side wall of said gate electrode; and

a metallic silicide layer having a second Ni as a main component which is provided over said gate electrode, and;

wherein said metal cap film is selectively provided over said second silicide layer provided over said gate electrode.

6. The semiconductor device according to claim 1,

wherein said gate insulation film includes a High-k film.

7. The semiconductor device according to claim 1,

wherein said gate insulation film is a two-layer structural film of a SiON film and a High-k film.

8. The semiconductor device according to claim 1,

wherein said metal cap film includes W and P.

9. The semiconductor device according to claim 7,

wherein said metal cap film includes palladium belonging to the same group in the periodic table as Ni included in said silicide layer.

10. A method of manufacturing a semiconductor device, comprising:

forming a gate insulation film over a semiconductor substrate;

forming a gate electrode over said gate insulation film;

forming a diffusion layer in the neighborhood of said gate electrode;

forming selectively a metallic silicide layer having Ni as a main component over said diffusion layer; and

growing selectively a metal cap film having Co as a main component over said metallic silicide layer.

11. The method of manufacturing a semiconductor device according to claim 10,

wherein said metallic silicide layer further includes Pt.

12. The method of manufacturing a semiconductor device according to claim 10,

wherein said step of growing selectively a metal cap film, comprises:

preprocessing during which a palladium solution is applied; and

growing selectively during which an alkali solution including Co being a main component of said metal cap film, is applied.

13. The method of manufacturing a semiconductor device according to claim 10, further comprising:

forming a side wall insulation film over the side wall of said gate electrode;

forming selectively a metallic silicide layer having a second Ni as a main component, over said gate electrode; and

growing selectively said metal cap film over said second silicide layer.

14. The method of manufacturing a semiconductor device according to claim 10,

wherein said step of forming a gate insulation film includes forming a High-k film.

15. The method of manufacturing a semiconductor device according to claim 10,

wherein said step of forming a gate insulation film includes forming a SiON film, and forming a High-k film.

16. The method of manufacturing a semiconductor device according to claim 10,

wherein Ni included in said silicide layer belongs to the same group in the periodic table as palladium used in said step of preprocessing.

17. The method of manufacturing a semiconductor device according to claim 10,

wherein said metal cap film includes W and P.