MULTI-DIRECTIONAL TRENCHING OF A DIE IN MANUFACTURING SUPERJUNCTION DEVICES

• US 20090085147A1
• Filed: 02/15/2008
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: IceMOS Technology Ltd
• Original Assignee: IceMos Technology Corp.
• Inventors: Sugiura, Kenji, Griffin, Hugh J., Ishiguro, Takeshi
• Granted Patent: US 8,012,806 B2
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Abstract

A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.

Claims

1. A method of manufacturing a superjunction device, the method comprising:

(a) providing a semiconductor wafer, the semiconductor wafer including at least one die;

(b) forming at least one first trench in the at least one die, the at least one first trench having a first orientation; and

(c) forming at least one second trench in the at least one die, the at least one second trench having a second orientation that is different from the first orientation.

2. The method of claim 1, wherein the at least one first trench defines a first area and the at least one second trench defines a second area.

3. The method of claim 2, wherein a ratio of the first area to the second area is one-to-one.

4. The method of claim 1, further comprising:

(d) forming at least one additional trench in the at least one die, each additional trench having an orientation that is different from at least one of the first orientation and the second orientation.

5. The method of claim 1, wherein the steps (a)-(c) are performed sequentially.

6. The method of claim 1, wherein the steps (b) and (c) are performed concurrently.

7. The method of claim 1, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is substantially completed.

8. The method of claim 1, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is fully completed.

9. A superjunction device formed by the method of claim 1.

10. A method of manufacturing a superjunction device, the method comprising:

(a) providing a semiconductor wafer, the semiconductor wafer including at least one die;

(b) forming a first plurality of trenches in the at least one die, each of the first plurality of trenches having a first orientation; and

(c) forming a second plurality of trenches in the at least one die, each of the second plurality of trenches having a second orientation that is different from the first orientation.

11. The method of claim 10, wherein the first plurality of trenches defines a first area and the second plurality of trenches defines a second area.

12. The method of claim 10, wherein a ratio of the first area to the second area is one-to-one.

13. The method of claim 10, wherein

(i) each of the first plurality of trenches has a length dimension, the length dimension of each of the first plurality of trenches being different from at least one other of the first plurality of trenches;

and

(ii) each of the second plurality of trenches has a length dimension, the length dimension of each of the second plurality of trenches being different from at least one other of the second plurality of trenches.

14. The method of claim 10, wherein

(i) each of the first plurality of trenches has a length dimension, the length dimension of each of the first plurality of trenches being identical;

and

(ii) each of the second plurality of trenches has a length dimension, the length dimension of each of the second plurality of trenches being identical.

15. The method of claim 10, wherein the steps (a)-(c) are performed sequentially.

16. The method of claim 10, wherein the steps (b) and (c) are performed concurrently.

17. The method of claim 10, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is substantially completed.

18. The method of claim 10, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is fully completed.

19. A super unction device formed by the method of claim 10.

20. A superjunction device comprising:

(a) a semiconductor wafer, the semiconductor wafer including at least one die;

(b) at least one first trench formed in the at least one die, the at least one first trench having a first orientation; and

(c) at least one second trench formed in the at least one die, the at least one second trench having a second orientation that is different from the first orientation.

21. The device of claim 20, wherein the at least one first trench defines a first area and the at least one second trench defines a second area.

22. The device of claim 20, wherein a ratio of the first area to the second area is one-to-one.