METAL SURFACE TREATMENTS FOR UNIFORMLY GROWING DIELECTRIC LAYERS

• US 20090085156A1
• Filed: 09/28/2007
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Dewey, Gilbert, Kavalieros, Jack, Metz, Matthew V.
• Application Number:
  US11/864,904
• Publication Number:
  US 20090085156A1
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

A fabrication process for a MIM capacitor comprises providing a substrate, depositing a first metal layer on a dielectric layer of the substrate, forming an interfacial layer on the first metal layer, wherein the interfacial layer has a hydroxyl terminated surface, depositing a capacitor dielectric layer on the interfacial layer using an ALD process, and depositing a second metal layer on the capacitor dielectric layer. The interfacial layer may be formed by depositing a thin layer of a metal oxide, by oxidizing a surface of the first metal layer with an oxygen plasma, or by evaporating a thin metal oxide onto the surface of the first metal layer.

Claims

1. A fabrication process for a MIM capacitor, comprising:

providing a substrate;

depositing a first metal layer on a dielectric layer of the substrate;

forming an interfacial layer on the first metal layer, wherein the interfacial layer has a hydroxyl terminated surface;

depositing a capacitor dielectric layer on the interfacial layer using an ALD process; and

depositing a second metal layer on the capacitor dielectric layer.

2. The method of claim 1, wherein the substrate includes a transistor for use in a 1T1C memory cell.

3. The method of claim 2, wherein the first metal layer is deposited on a portion of the dielectric layer that includes a via that electrically couples the first metal layer to the transistor.

4. The method of claim 1, wherein the forming of the interfacial layer comprises depositing a thin layer of a metal oxide having a thickness less than or equal to 6 Å

onto the first metal layer, wherein the metal oxide is selected from the group consisting of titanium oxide, tantalum oxide, and titanium oxynitride.

5. The method of claim 1, wherein the forming of the interfacial layer comprises oxidizing a surface of the first metal layer with an oxygen plasma.

6. The method of claim 1, wherein the forming of the interfacial layer comprises evaporating a thin metal oxide onto the surface of the first metal layer, wherein the metal oxide is selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, and tantalum oxide.

7. A MIM capacitor comprising:

a semiconductor substrate;

a first metal layer on the semiconductor substrate;

an interfacial layer on the first metal layer, wherein the interfacial layer has a hydroxyl terminated surface;

a capacitor dielectric layer on the hydroxyl terminated surface of the interfacial layer; and

a first metal layer on the capacitor dielectric layer.

8. The MIM capacitor of claim 7, wherein the substrate includes:

a transistor for use in a 1T1C memory cell; and

a via that electrically couples the transistor to the first metal layer.

9. The MIM capacitor of claim 7, wherein the first metal layer comprises at least one metal selected from the group consisting of copper, aluminum, magnesium, tin, zirconium, indium, tungsten, and silver.

10. The MIM capacitor of claim 7, wherein the first metal layer has a thickness that ranges between around 1 nm and around 100 nm.

11. The MIM capacitor of claim 7, wherein the interfacial layer is selected from the group consisting of titanium oxide, tantalum oxide, titanium oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and tantalum oxide.

12. The MIM capacitor of claim 7, wherein the interfacial layer has a thickness that ranges up to around 6 Å

.

13. The MIM capacitor of claim 7, wherein the capacitor dielectric layer is selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

14. The MIM capacitor of claim 7, wherein the capacitor dielectric layer has a thickness that ranges between around 3 nm and around 20 nm.

15. The MIM capacitor of claim 7, wherein the second metal layer comprises at least one metal selected from the group consisting of copper, aluminum, magnesium, tin, zirconium, indium, tungsten, and silver.

16. The MIM capacitor of claim 7, wherein the second metal layer has a thickness that ranges between around 1 nm and around 100 nm.