Semiconductor packages having interposers, electronic products employing the same, and methods of manufacturing the same

• US 20090085225A1
• Filed: 10/01/2008
• Published: 04/02/2009
• Est. Priority Date: 10/02/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Sung-Yong
• Granted Patent: US 8,093,726 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor package and methods for manufacturing the same are provided. The semiconductor package includes a substrate, first and second semiconductor chips stacked on the substrate. An interposer is disposed between the first and second semiconductor chips. The interposer has a non-planar top surface.

Claims

1. A semiconductor package comprising:

a substrate;

first and second semiconductor chips stacked on the substrate; and

a first interposer between the first and second semiconductor chips, the first interposer having a first non-planar top surface.

2. The semiconductor package of claim 1, wherein the first non-planar top surface comprises a stepped region defining a first region and a second region, and wherein the second region is thinner than the first region to define a recessed region on the second region.

3. The semiconductor package of claim 2, wherein the second semiconductor chip is stacked on the second region.

4. The semiconductor package of claim 2, wherein the first interposer comprises a circuit pattern disposed in one of the first and second regions.

5. The semiconductor package of claim 2, wherein the first interposer has a rectangular shape including four corners, the second region is disposed to include only one corner of the first interposer and the first region is disposed to include three corners of the first interposer.

6. The semiconductor package of claim 2, wherein the second region is disposed at a central part of the first interposer and the first region surrounds the second region.

7. The semiconductor package of claim 2, wherein the first region includes two separated regions and the second region is disposed between the two separated regions.

8. The semiconductor package of claim 2, wherein the second region is disposed only at one side of the first region.

9. The semiconductor package of claim 2, wherein the second semiconductor chip vertically protrudes from a top surface of the first region.

10. The semiconductor package of claim 2, wherein the second semiconductor chip laterally extends to have an overhang the first semiconductor chip.

11. The semiconductor package of claim 10, further comprising a gap between the first semiconductor chip and the overhang of the second semiconductor chip, wherein the gap has a vertical width substantially equal to a thickness of the second region of the first interposer.

12. The semiconductor package of claim 11, further comprising a bonding wire electrically connecting the substrate to the first semiconductor chip, wherein the bonding wire is disposed in the gap.

13. The semiconductor package of claim 1, wherein the first semiconductor chip is electrically and directly connected to the substrate, wherein the first interposer is electrically and directly connected to the substrate, and wherein the second semiconductor is electrically connected to the substrate through the first interposer.

14. The semiconductor package of claim 13, wherein the second semiconductor chip is also electrically and directly connected to the substrate.

15. The semiconductor package of claim 1, further comprising:

a third semiconductor chip stacked on the second semiconductor chip; and

a second interposer disposed between the second semiconductor chip and the third semiconductor- chip to electrically connect the third semiconductor chip to the substrate, the second interposer having a second non-planar top surface.

16. A semiconductor package comprising:

a first semiconductor package including a first semiconductor chip, a second semiconductor chip and a first interposer between the first and second semiconductor chips, the first interposer having a first non-planar top surface; and

a second semiconductor package stacked on the first semiconductor package, the second semiconductor package including a third semiconductor chip, a fourth semiconductor chip and a second interposer between the third and fourth semiconductor chips, the second interposer having a second non-planar top surface.

17. A method of manufacturing a semiconductor package, the method comprising:

providing a substrate;

mounting a first semiconductor chip on the substrate to electrically connect the first semiconductor chip to the substrate;

mounting a first interposer on the first semiconductor chip to electrically connect the first interposer to the substrate, wherein the first interposer comprises a first region and a second region which is lower than the first region; and

mounting a second semiconductor chip on the second region of the first interposer to electrically connect the second semiconductor chip to the first interposer.

18. The method of claim 17, wherein mounting the second semiconductor chip comprises electrically connecting the second semiconductor chip to the substrate through the first interposer.

19. The method of claim 18, wherein mounting the second semiconductor chip further comprises electrically and directly connecting the second semiconductor chip to the substrate.

20. The method of claim 17, further comprising:

mounting a second interposer on the second semiconductor chip to electrically connect the second interposer to the substrate, wherein the second interposer comprises a first region and a second region which is lower than the first region; and

mounting a third semiconductor chip on the second region of the second interposer to electrically connect the third semiconductor chip to the second interposer.