Method And Apparatus For Testing Devices Using Serially Controlled Intelligent Switches

• US 20090085590A1
• Filed: 09/27/2007
• Published: 04/02/2009
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Berry, Tommie Edward, Sporck, A. Nicholas
• Granted Patent: US 7,977,959 B2
• Time in Patent Office: Days
• US Class Current: 324/754.70
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

Methods and apparatus for testing devices using serially controlled intelligent switches have been described. In some embodiments, a probe card assembly can be provided that includes a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line.

Claims

1. A probe card assembly, comprising:

a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line.

2. The probe card assembly of claim 1, wherein each of the plurality of ICs includes a shift register configured to store bits of a control word provided by the control signal.

3. The probe card assembly of claim 2, wherein each of the plurality of ICs includes control logic, the shift register driving the control logic to program the plurality of switches.

4. The probe card assembly of claim 1, wherein each of the switches is configured to open responsive to a programmable current level.

5. The probe card assembly of claim 4, wherein each of the switches is configured to open responsive to the programmable current level existing for a programmable debounce period.

6. The probe card assembly of claim 1, wherein each of the switches comprises:

a switch circuit having a first terminal, a second terminal, and a control terminal;

a current sensor coupled to each of the first terminal and the second terminal, the current sensor having an output terminal; and

debounce logic coupled between the control terminal of the switch circuit and the output terminal of the current sensor.

7. The probe card assembly of claim 1, wherein each of the plurality of ICs includes at most four of the switches.

8. A test assembly, comprising:

a printed wiring board including connectors for connecting to test instruments, and a serial control line providing a control signal;

a probe head supporting test probes; and

at least one integrated circuit (IC) coupled to the serial control line, the at least one IC including switches coupled to at least a portion of the test probes, each of the switches being programmable responsive to the control signal transmitted as a sequential bit stream on the serial control line.

9. The test assembly of claim 8, wherein the at least one IC includes a plurality of ICs coupled to form a chain, the chain coupled to the serial control line.

10. The test assembly of claim 8, wherein the at least one IC is mounted on the printed wiring board.

11. The test assembly of claim 8, wherein the at least one IC is mounted on the probe head.

12. The test assembly of claim 8, wherein at least one of the switches is configured to switch a test signal applied to one of test probes by the test instruments.

13. The test assembly of claim 8, wherein at least one of the switches is configured to switch a test signal applied to the test instruments by one of the test probes.

14. The test assembly of claim 8, where each of the switches is configured to open responsive to a programmable current level existing for a programmable debounce period.

15. A method of testing components on a wafer using a probe card assembly, comprising:

serially shifting a control signal through a chain comprising a plurality of integrated circuits (ICs) including a plurality of switches, the plurality of switches being programmed responsive to the control signal; and

communicating test signals between test probes and test instruments through the plurality of switches to test the components.

16. The method of claim 15, wherein the act of serially shifting comprises:

loading first bits of the control signal into a shift register of each of the plurality of ICs, the first bits selectively enabling a programmable current trip and a current sensing capability for each of the plurality of switches.

17. The method of claim 16, wherein the act of serially shifting further comprises:

loading second bits of the control signal into the shift register of each of the plurality of ICs, the second bits programming a current threshold of the programmable current trip for each of the plurality of switches.

18. The method of claim 17, wherein the act of serially shifting further comprises:

loading third bits of the control signal into the shift register of each of the plurality of ICs, the third bits programming a debounce time of the programmable current trip for each of the plurality of switches.

19. The method of claim 15, wherein the act of serially shifting comprises loading bits of the control signal into a shift register of each of the plurality of ICs, the bits causing calibration of a current sensing capability of each of the plurality of switches.

20. The method of claim 15, further comprising:

capturing a readback signal from the chain, the read back signal including bits indicative of status for each of the plurality of switches.

21. -37. (canceled)