Systems, methods and devices for arbitrating die stack position in a multi-bit stack device
First Claim
1. A stacked die device having a plurality of semiconductor devices, comprising:
- an electrical node;
a first semiconductor device having a plurality of terminals, one of which is coupled to the node, the first device having an output buffer configured to generate and provide an output signal to the terminal coupled to the node in response to an input signal, the first device further having an arbitration circuit coupled to the input of the output buffer and the node and configured to compare the logic states of the input signal and the node and generate a signal indicative of a mismatch; and
a second semiconductor device having a plurality of terminals, one of which is coupled to the node, the second device having an output buffer configured to generate and provide an output signal to the terminal coupled to the node in response to an input signal, the second device further having an arbitration circuit coupled to the input of the output buffer and the node and configured to compare the logic states of the input signal and the node and generate a signal indicative of a mismatch.
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0 Petitions
Accused Products
Abstract
Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked dies are arbitrated to select one of the dies as the primary die and the other as secondary. Each die includes an input/output buffer that drives an output signal to a commonly shared output terminal in response to receiving a die identification data bit as the input signal. Each die also includes an arbitration circuit that generates a control signal in response to the identification bit of one die being mismatched to a corresponding identification bit of the other die. The control signal programs a stack enable fuse in accordance with the arbitration to designate one of the dies as the secondary die.
85 Citations
29 Claims
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1. A stacked die device having a plurality of semiconductor devices, comprising:
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an electrical node; a first semiconductor device having a plurality of terminals, one of which is coupled to the node, the first device having an output buffer configured to generate and provide an output signal to the terminal coupled to the node in response to an input signal, the first device further having an arbitration circuit coupled to the input of the output buffer and the node and configured to compare the logic states of the input signal and the node and generate a signal indicative of a mismatch; and a second semiconductor device having a plurality of terminals, one of which is coupled to the node, the second device having an output buffer configured to generate and provide an output signal to the terminal coupled to the node in response to an input signal, the second device further having an arbitration circuit coupled to the input of the output buffer and the node and configured to compare the logic states of the input signal and the node and generate a signal indicative of a mismatch. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor stacked die device, comprising:
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a host die having a first identifier signal, the first die being coupled to an output terminal; and at least another die stacked over the host die, the at least another die having a second identifier signal and being coupled to the output terminal, each of the dies comprising; an input/output buffer having an input terminal that receives the identifier signal from the respective die, the input/output buffer operable to drive an output signal to the output terminal in response to receiving the identifier signal; and an arbitration block coupled to the input/output buffer, the arbitration block operable to receive and compare the identifier signal and the output signal, the arbitration block further operable to generate a control signal responsive to the identifier signal of its host die being mismatched to the identifier signal of the at least another die and the output signal of the at least another die overriding the output signal of the host die at the output terminal. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A plurality of stacked dies in a memory device, each of the stacked die comprising:
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an input terminal configured to receive an input signal; an output terminal coupled to at least another stacked die in the plurality of stacked dies; an output driver configured to receive the input signal and operable to drive an output signal to the output terminal in response to the input signal; and an arbitration circuit coupled to the output driver and the input terminal, the arbitration circuit having a logic gate and a latch circuit, the logic gate of the arbitration circuit operable to compare the input signal and the output signal, and further operable to enable the latch circuit to latch a stack control signal when the drive strength of the output driver is less than the driver strength of an output driver of the at least another stacked die. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A processor-based system comprising:
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a data input device; a data output device; a plurality of buses to and from the data input, output and storage devices; processor circuitry coupled to the data input, output and storage devices, the processor circuitry operable to process data to and from the data input and output devices on the plurality of buses; and at least one multi-die memory device comprising; a host die having a first input signal, the first die being coupled to the processor circuitry and to an output terminal coupled to at least one of the plurality of buses; and at least another die stacked on top of the host die, the at least another die having a second input signal and being coupled to the processor circuitry and to the output terminal of the host die, each of the dies comprising; an input/output buffer having an input terminal to receive the input signal from the respective die, the input/output buffer operable to drive a first output signal to the output terminal responsive to receiving the first input signal; and an arbitration circuit coupled to the input/output buffer, the arbitration circuit, responsive to a test mode of operation, configured to receive the respective first input signal and the first output signal, the arbitration circuit operable to compare the received signals and generate a fuse control signal responsive to the first input signal of the host die being mismatched to the second input signal of the at least another die and the second output signal of the at least another die overriding the first output signal of the host die at the output terminal. - View Dependent Claims (22, 23)
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24. A method of programming pins of at least two semiconductor dies, comprising:
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driving a first output signal at a first drive strength in response to receiving a first input signal; driving a second output signal at a second drive strength in response to receiving a second input signal; arbitrating between the first and second input signals to determine which of the first and second output signals is generated from the stronger drive strength; and latching a fuse control signal to program a stack enable fuse that designates a primary die assignment and a secondary die assignment based on the arbitration. - View Dependent Claims (25, 26)
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27. A method of assigning pins of a stacked multi-die semiconductor device, comprising:
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entering a stack test mode of operation; simultaneously executing a first die identification read operation and at least a second die identification read operation in response to entering the stack test mode of operation; arbitrating data bits between the first die identification and the at least second die identification to determine a data bit in the first die identification having a value that is opposite to a value of a corresponding data bit in the second die identification; selecting one of the data bits as losing the arbitration; entering a program fuse mode of operation in response to selecting the losing bit; and programming a stack enable fuse to assign a secondary pin assignment to the losing bit. - View Dependent Claims (28, 29)
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Specification