High Voltage Generation and Control in Source-Side Injection Programming of Non-Volatile Memory

• US 20090086542A1
• Filed: 09/28/2007
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Lee, Dana, So, Hock
• Granted Patent: US 7,894,263 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/565 Multilevel memory comprising elements in triple well structure

Abstract

Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.

Claims

1. A method of programming non-volatile memory, comprising:

providing a first voltage to a first bit line adjacent to a second bit line;

providing a second voltage to the second bit line after providing the first voltage to the first bit line to boost the first bit line above a level of the first voltage;

providing a third voltage to a gate region of a selected non-volatile storage element in communication with the first bit line;

injecting electrons from a source side of the selected storage element into a charge storage region of the storage element.

2. The method of claim 1, further comprising:

providing a fourth voltage to a gate region of an unselected non-volatile storage element adjacent to the selected non-volatile storage element while providing the first voltage, the second voltage, and the third voltage.

3. The method of claim 2, wherein:

providing the fourth voltage induces hot carrier injection of the electrons from the source side of the selected storage element into the charge storage region.

4. The method of claim 3, wherein:

providing the fourth voltage induces hot carrier injection of the electrons from a drain side of the unselected storage element into the charge storage region of the selected storage element; and

the drain side of the unselected storage element and the source side of the selected storage element are a common electrical node.

5. The method of claim 2, wherein:

the unselected non-volatile storage element is a hot carrier injector providing the electrons from a drain side of the unselected storage element to the source side of the selected storage element.

6. The method of claim 2, wherein the first bit line is in communication with a first NAND string, the first NAND string includes the selected storage element and the unselected storage element.

7. The method of claim 2, wherein the selected storage element and the unselected storage element are multi-state flash memory cells.

8. A method of programming non-volatile memory, comprising:

boosting a selected bit line above an applied voltage level by coupling to the selected bit line a portion of a second voltage applied to a different electrical node of the memory;

applying a program voltage to a selected word line during at least a portion of the boosting;

programming a selected non-volatile storage element in communication with the selected bit line and the selected word line by injecting electrons from a source side of the selected non-volatile storage element into a charge storage region of the non-volatile storage element.

9. The method of claim 8, wherein the different electrical node is an adjacent unselected bit line.

10. The method of claim 8, wherein the different electrical node is a well region associated with a group of storage elements including the selected storage element.

11. The method of claim 8, wherein:

injecting electrons from the source side of the selected non-volatile storage element includes injecting electrons from a drain side of an unselected non-volatile storage element in communication an unselected word line adjacent to the selected word line.

12. The method of claim 11, further comprising:

applying a positive voltage to the unselected word line while applying the program voltage to the selected word line.

13. The method of claim 8, further comprising:

increasing the positive voltage applied to the unselected word line while applying the program voltage to the selected word line;

14. The method of claim 13, wherein applying the positive voltage and increasing the positive voltage includes sweeping the unselected word line from a ground potential to a read voltage, the read voltage is a voltage sufficient to turn on a storage element programmed to a highest level state associated with the non-volatile memory.

15. The method of claim 8, further comprising:

discharging the selected bit line prior to applying the positive bias to the unselected word line when the unselected non-volatile storage element is in an erased state; and

discharging the selected bit line as a result of increasing the positive voltage when the unselected non-volatile storage element is in a programmed state.

16. A method of programming non-volatile storage, comprising:

charging a first set of bit lines;

boosting the first set of bit lines above a voltage level resulting from the charging by applying a first voltage to a second set of bit lines, wherein each bit line of the first set is adjacent to one or more bit lines of the second set;

applying a programming voltage to a selected word line while boosting the first set of bit lines;

programming one or more non-volatile storage elements in communication with the selected word line as a result of boosting the first set of bit lines and applying the programming voltage to the selected word line, the one or more non-volatile storage elements are each in communication with one bit line from the first set of bit lines.

17. The method of claim 16, further comprising:

prior to boosting the first set of bit lines, applying a second voltage to a first source line, the first source line is associated with the first set of bit lines;

lowering a magnitude of the second voltage while boosting the first set of bit lines to enable programming of the one or more non-volatile storage elements.

18. The method of claim 17, further comprising:

applying a third voltage to a second source line while applying the first voltage to the second set of bit lines to inhibit programming of non-volatile storage elements in communication with the selected word line and the second set of bit lines, the third voltage is equal to the first voltage.

19. The method of claim 16, further comprising:

applying a second voltage to an unselected word line, the unselected word line is adjacent to the selected word line in a source direction.

20. The method of claim 19, further comprising:

increasing a magnitude of the second voltage from a first level to a second level.

21. The method of claim 20, wherein:

increasing the magnitude of the second voltage includes sweeping the second voltage from the first level to the second level.

22. The method of claim 20, wherein:

programming one or more non-volatile storage elements includes programming a first storage element prior to increasing the magnitude of the second voltage;

programming the first storage element includes discharging a first bit line of the first set, the first bit line is in communication with the first storage element.

23. The method of claim 20, wherein:

programming one or more non-volatile storage elements includes programming a first non-volatile storage element after the magnitude of the second voltage is increased from an initial magnitude; and

programming the first non-volatile storage element includes discharging a first bit line of the first set, the first bit line is in communication with the first storage element.

24. The method of claim 16, further comprising:

providing an inhibit voltage to a third set of bit lines while boosting the first set of bit lines and applying the programming voltage, wherein each bit line of the third set is adjacent to one or more bit lines of the second set.

25. The method of claim 24, wherein:

the first set of bit lines and the third set of bit lines comprises a set of odd bit lines; and

the second set of bit lines comprises a set of even bit lines.

26. A non-volatile memory system, comprising:

a first bit line;

a second bit line adjacent to the first bit line;

a selected non-volatile storage element in communication with the first bit line, the selected non-volatile storage element including a charge storage region;

managing circuitry in communication with the first bit line, the second bit line, and the selected non-volatile storage element that programs the selected storage element by providing a first voltage to the first bit line, providing a second voltage to the second bit line after providing the first voltage to the first bit line to boost the first bit line above a level of the first voltage, providing a third voltage to the gate region of the selected storage element, and injecting electrons from a source side of the selected storage element into the charge storage region of the storage element.

27. The non-volatile memory system of claim 26, further comprising:

an unselected non-volatile storage element adjacent to the selected non-volatile storage element, the unselected storage element is in communication with the first bit line;

the managing circuitry provides a fourth voltage to a gate region of the unselected storage element while providing the first voltage, the second voltage, and the third voltage.

28. The non-volatile memory system of claim 27, wherein:

providing the fourth voltage induces hot carrier injection of the electrons from the source side of the selected storage element into the charge storage region.

29. The non-volatile memory system of claim 28, wherein:

providing the fourth voltage induces hot carrier injection of the electrons from a drain side of the unselected storage element into the charge storage region of the selected storage element; and

the drain side of the unselected storage element and the source side of the selected storage element are a common electrical node.

30. The non-volatile memory system of claim 27, wherein:

the unselected non-volatile storage element is a hot carrier injector providing the electrons from a drain side of the unselected storage element to the source side of the selected storage element.

31. The non-volatile memory system of claim 27, wherein the first bit line is in communication with a first NAND string, the first NAND string includes the selected storage element and the unselected storage element.

32. The non-volatile memory system of claim 27, wherein the selected storage element and the unselected storage element are multi-state flash memory cells.

33. The non-volatile memory system of claim 26, wherein the managing circuitry includes a state machine.

34. The non-volatile memory system of claim 33, wherein the managing circuitry further includes row control circuitry and column control circuitry.

35. A non-volatile memory system, comprising:

a first bit line;

a first word line;

a selected non-volatile storage element in communication with the first bit line and the first word line, the selected storage element including a charge storage region;

managing circuitry that boosts the first bit line above an applied voltage level by coupling to the first bit line a portion of a second voltage applied to a different electrical node of the memory system, the managing circuitry applies a program voltage to the selected word line during at least a portion of the boosting and programs the selected storage element by injecting electrons from a source side of the selected non-volatile storage element into the charge storage region.

36. The non-volatile memory system of claim 35, wherein the different electrical node is an unselected bit line adjacent to the first bit line.

37. The non-volatile memory system of claim 35, wherein the different electrical node is a well region associated with a group of storage elements including the selected storage element.

38. The non-volatile memory system of claim 35, further comprising:

a second word line adjacent to the first word line in a source direction;

an unselected non-volatile storage element in communication with the second word line;

wherein injecting electrons from the source side of the selected non-volatile storage element includes injecting electrons from a drain side of the unselected storage element.

39. The non-volatile memory system of claim 35, wherein the managing circuitry applies a positive voltage to the second word line while applying the program voltage to the first word line.

40. The non-volatile memory system of claim 35, wherein the managing circuitry increases the positive voltage applied to the second word line while applying the program voltage to the first word line.

41. The non-volatile memory system of claim 40, wherein the managing circuitry increases the positive voltage by sweeping the second word line from a ground potential to a read voltage, the read voltage is a voltage sufficient to turn on a non-volatile storage element programmed to a highest level state associated with the non-volatile memory system.

42. The non-volatile memory system of claim 35, wherein:

the managing circuitry discharges the first bit line prior to applying the positive voltage to the second word line when the unselected non-volatile storage element is in an erased state; and

the managing circuitry discharges the first bit line as a result of increasing the positive voltage when the unselected non-volatile storage element is in a programmed state.

43. A non-volatile memory system, comprising:

a first word line;

a first set of bit lines;

a second set of bit lines, each bit line of the first set is adjacent to one or more bit lines of the second set;

a plurality of non-volatile storage elements in communication with the first word line, each non-volatile storage element of the plurality is in communication with one bit line from the first set of bit lines;

managing circuitry in communication with the first word line, the first set of bit lines, and the second set of bit lines, the managing circuitry charges the first set of bit lines, boosts the first set of bit lines above a voltage level resulting from the charging by applying a first voltage to the second set of bit lines, applies a programming voltage to the selected word line while boosting the first set of bit lines, and programs one or more of the non-volatile storage elements as a result of boosting the first set of bit lines and applying the programming voltage to the selected word line.

44. The non-volatile memory system of claim 43, further comprising:

a first source line associated with the first set of bit lines;

the managing circuitry applies a second voltage to the first source line and then lowers a magnitude of the second voltage while boosting the first set of bit lines to enable programming of the one or more non-volatile storage elements.

45. The non-volatile memory system of claim 44, further comprising:

a second source associated with the second set of bit lines;

the managing circuitry applies a third voltage to the second source line while applying the first voltage to the second set of bit lines to inhibit programming of non-volatile storage elements in communication with the first word line and the second set of bit lines, the third voltage is equal to the first voltage.

46. The non-volatile memory system of claim 43, further comprising:

a second word line adjacent to the first word line in a source direction;

the managing circuitry applies a second voltage to the second word line.

47. The non-volatile memory system of claim 46, wherein the managing circuitry increases a magnitude of the second voltage from a first level to a second level by sweeping the second voltage from the first level to the second level.

48. The non-volatile memory system of claim 47, wherein:

the one or more non-volatile storage elements includes a first non-volatile storage element, the first non-volatile storage element is in communication with a first bit line of the first set of bit lines;

the one or more non-volatile storage elements includes a second non-volatile storage element, the second non-volatile storage element is in communication with a second bit line of the first set of bit lines;

the managing circuitry programs the first storage element prior to increasing the magnitude of the second voltage, the managing circuitry discharges the first bit line when programming the first storage element; and

the managing circuitry programs the second storage element after a magnitude of the second voltage is increased from an initial magnitude, the managing circuitry discharges the second bit line when programming the second storage element.

49. The non-volatile memory system of claim 43, wherein:

the managing circuitry provides an inhibit voltage to a third set of bit lines while boosting the first set of bit lines and applying the programming voltage, wherein each bit line of the third set is adjacent to one or more bit lines of the second set.

50. The non-volatile memory system of claim 49, wherein:

the first set of bit lines and the third set of bit lines comprise a set of even bit lines; and

the second set of bit lines comprises a set of odd bit lines.

51. A method of programming non-volatile memory, comprising:

pre-charging a bit line associated with a group of non-volatile storage elements based on a current threshold voltage of a selected non-volatile storage element of the group;

boosting the bit line above a voltage level resulting from the pre-charging; and

programming the selected non-volatile storage element by discharging the bit line through the group of non-volatile storage elements while applying a programming voltage to the selected storage element.

52. The method of claim 51, wherein programming the selected storage element comprises injecting electrons at a source side of a floating gate of the selected storage element.

53. The method of claim 51, wherein pre-charging the bit line includes:

applying a pre-charge voltage to a source line associated with the group of storage elements;

applying a target threshold voltage to the selected storage element;

charging the bit line to the pre-charge voltage level when a difference between the target threshold voltage and the current threshold voltage is larger than the pre-charge voltage; and

charging the bit line to a level of the difference between the target threshold voltage and the current threshold voltage when the level of the difference is less than the pre-charge voltage level.

54. The method of claim 53, wherein applying the pre-charge voltage and the target threshold voltage are performed as part of analog sensing the current threshold voltage of the selected storage element by drain source reverse readout.

55. The method of claim 51, wherein:

the group of non-volatile storage elements is a NAND string;

the NAND string is part a memory array including a plurality of NAND strings;

a plurality of word lines connect to the memory array;

the bit line is part of a first subset of bit lines connecting to a first subset of NAND strings of the plurality;

a second subset of bit lines is interleaved with the first subset and includes a second subset of NAND strings of the plurality; and

a first source line connects to the first subset of NAND strings and a second source connects to the second subset of NAND strings.

56. The method of claim 55, wherein boosting the bit line includes:

applying a boosting voltage to the second subset of bit lines.

57. The method of claim 56, further comprising:

applying the boosting voltage to the second source line to inhibit programming in the second subset of NAND strings.

58. The method of claim 57, wherein boosting the bit line includes:

raising the bit line from the pre-charge level to a boosted potential through capacitive coupling with at least one bit line of the second subset of bit lines.

59. A method of programming non-volatile storage, comprising:

applying a first voltage to a source line associated with a group of non-volatile storage elements;

applying a target voltage to a selected storage element of the group while the group of storage elements is open to the source line;

charging the bit line while the target voltage is applied to the selected storage element;

boosting the bit line above a voltage level resulting from charging; and

applying a programming voltage to the selected storage element with the group of storage elements open to the bit line to program the selected storage element by source side injection.

60. The method of claim 59, wherein charging the bit line while applying the target voltage comprises charging the bit line based on a current level of programming associated with the selected storage element.

61. The method of claim 59, wherein charging the bit line includes:

charging the bit line to a level of the first voltage when a difference between a current threshold voltage of the selected storage element and the target voltage is greater than the first voltage; and

charging the bit line to a level based on the difference between the target voltage and the current threshold voltage of the selected storage element when the difference is less than the first voltage.

62. The method of claim 59, wherein the target voltage is a verify level associated with a target state for the selected storage element.

63. The method of claim 59, wherein:

the selected storage element is coupled to a selected word line;

the selected word line is coupled to a plurality of additional non-volatile storage elements, the selected word line receives the target voltage and programming voltage for application to the selected storage element; and

the method further comprises;

verifying whether the selected storage element has reached a target state associated with the target voltage after programming the selected storage element,

repeating said applying a first voltage, applying a target voltage, charging the bit line, boosting the bit line and applying the programming voltage if the selected storage element has not reached the target state, and

applying an inhibit voltage to the bit line while repeating said applying the target voltage and applying the programming voltage during programming for one or more of the additional storage elements if the selected storage element has reached the target state.

64. The method of claim 63, wherein applying the programming voltage during said repeating includes increasing a magnitude of said programming voltage by a pre-determined step size.

65. The method of claim 59, wherein boosting the bit line above the voltage level resulting from charging the bit line includes applying a boosting voltage to a second bit line adjacent to the selected bit line.

66. The method of claim 65, wherein:

the second bit line is capacitively coupled to the selected bit line

the selected bit line is boosted above the voltage level resulting from charging by an amount based on the capacitively coupling and a magnitude of the boosting voltage.

67. The method of claim 59, wherein:

the bit line is part of a first set of bit lines;

boosting the bit line voltage includes holding the voltage level resulting from charging on the bit line, applying a boosting voltage to a second set of bit lines formed adjacent to and between the first set of bit lines, and allowing the voltage level of the bit line to rise in accordance with the boosting voltage applied to the second set of bit lines.

68. The method of claim 67, wherein the voltage level of the bit line rises in relation to the boosting voltage and a level of capacitively coupling existing between the first set of bit lines and the second set of bit lines.

69. A method of programming non-volatile memory, comprising:

sensing a threshold voltage of a selected storage element of a group of storage elements;

charging a bit line associated with the selected storage element based on the threshold voltage of the selected storage element;

boosting a voltage of the bit line after charging; and

transferring at least a portion of the voltage of the bit line into a channel region of the group of storage elements to program the selected storage element by source side injection.

70. The method of claim 69, wherein sensing a threshold voltage comprises sensing an analog threshold voltage of the selected storage element.

71. The method of claim 69, wherein sensing an analog threshold voltage comprises sensing the analog threshold voltage by drain source reverse readout.

72. The method of claim 71, wherein sensing the analog threshold voltage by drain source reverse readout includes:

applying a first voltage to a source line for the group of storage elements;

applying a pass voltage to unselected storage elements of the group;

opening the group of storage elements to the bit line and the source line; and

applying a target threshold voltage to the selected storage element.

73. The method of claim 72, wherein charging the bit line includes:

charging the bit line to the first voltage level when a difference between the target threshold voltage and an actual threshold voltage of the selected storage element is greater than the first voltage level; and

charging the bit line to a level of the difference between the target threshold voltage and the actual threshold voltage when the difference is less than the first voltage level.

74. A non-volatile memory system, comprising:

a bit line;

a group of non-volatile storage elements in communication with the bit line;

managing circuitry in communication with the group of non-volatile storage elements and the bit line, the managing circuitry programs a selected storage element of the group by pre-charging the bit line based on a current threshold voltage of the selected storage element, boosting the bit line above a voltage level resulting from the pre-charging, and programming the selected non-volatile storage element by discharging the bit line through the group of storage elements while applying a programming voltage to the selected storage element.

75. The non-volatile memory system of claim 74, wherein the managing circuitry programs the selected storage element by injecting electrons at a source side of a floating gate of the selected storage element.

76. The non-volatile memory system of claim 74, further comprising:

a source line associated with the group of storage elements;

wherein the managing circuitry pre-charges the bit line by applying a pre-charge voltage to the source line, applying a target threshold voltage to the selected storage element, charging the bit line to the pre-charge voltage level when a difference between the target threshold voltage and the current threshold voltage is larger than the pre-charge voltage, and charging the bit line to a level of the difference between the target threshold voltage and the current threshold voltage when the level of the difference is less than the pre-charge voltage level.

77. The non-volatile memory system of claim 76, wherein the managing circuitry applies the pre-charge voltage and the target threshold voltage as part of an analog sensing of the current threshold voltage of the selected storage element by drain source reverse readout.

78. The non-volatile memory system of claim 74, wherein:

the group of non-volatile storage elements is a NAND string;

the NAND string is part a memory array including a plurality of NAND strings;

a plurality of word lines connect to the memory array;

the bit line is part of a first subset of bit lines connecting to a first subset of NAND strings of the plurality;

a second subset of bit lines is interleaved with the first subset and includes a second subset of NAND strings of the plurality; and

a first source line connects to the first subset of NAND strings and a second source line connects to the second subset of NAND strings.

79. The non-volatile memory system of claim 78, wherein the managing circuitry boosts the bit line by applying a boosting voltage to the second subset of bit lines.

80. The non-volatile memory system of claim 79, wherein the managing circuitry applies the boosting voltage to the second source line to inhibit programming in the second subset of NAND strings.

81. The non-volatile memory system of claim 80, wherein the managing circuitry boosts the bit line by raising the bit line from the pre-charge level to a boosted potential through capacitive coupling with at least one bit line of the second subset of bit lines.

82. A non-volatile memory system, comprising:

a group of non-volatile storage elements;

a source line associated with the group of storage elements;

a bit line associated with the group of storage elements;

managing circuitry in communication with the group, the source line, and the bit line, the managing circuitry programs a selected storage element of the group by source side injection, the managing circuitry applies a first voltage to the source line, applies a target voltage to a selected storage element of the group while the group of storage elements is open to the source line, charges the bit line while the target voltage is applied to the selected storage element, boosts the bit line above a voltage level resulting from charging, and applies a programming voltage to the selected storage element with the group of storage elements open to the bit line to program the selected memory.

83. The non-volatile memory system of claim 82, wherein the managing circuitry charges the bit line based on a current level of programming associated with the selected memory cell.

84. The non-volatile memory system of claim 83, wherein the managing circuitry charges the bit line based on a current level of programming associated with the selected storage element by charging the bit line to a level of the first voltage when a difference between a current threshold voltage of the selected memory cell and the target voltage is greater than the first voltage, and charging the bit line to a level based on the difference between the target voltage and the current threshold voltage of the selected memory cell when the difference is less than the first voltage.

85. The non-volatile memory system of claim 82, wherein the target voltage is a verify level associated with a target state for the selected storage element.

86. The non-volatile memory system of claim 82, wherein:

the selected storage element is coupled to a selected word line;

the selected word line is coupled to a plurality of additional non-volatile storage elements;

the managing circuitry applies the target voltage to the selected word line and applies the programming voltage to the selected word line;

the managing circuitry verifies whether the selected storage element has reached a target state associated with the target voltage after programming the selected storage element and repeats applying the first voltage, applying the target voltage, charging the bit line, boosting the bit line and applying the programming voltage if the selected storage element has not reached the target state;

the managing circuitry applies an inhibit voltage to the bit line while repeating applying the target voltage and applying the programming voltage during programming for one or more of the additional storage elements if the selected storage element has reached the target state.

87. The non-volatile memory system of claim 86, wherein the managing circuitry increases a magnitude of the programming voltage by a pre-determined step size when applying the programming voltage during the repeating.

88. The non-volatile memory system of claim 82, wherein the managing circuitry boosts the bit line above the voltage level resulting from charging the bit line by applying a boosting voltage to a second bit line adjacent to the selected bit line.

89. The non-volatile memory system of claim 88, wherein:

the second bit line is capacitively coupled to the selected bit line

the selected bit line is boosted above the voltage level resulting from charging by an amount based on the capacitively coupling and a magnitude of the boosting voltage.

90. The non-volatile memory system of claim 82, wherein:

the bit line is part of a first set of bit lines;

the managing circuitry boosts the bit line voltage by holding the voltage level resulting from charging on the bit line, applying a boosting voltage to a second set of bit lines formed adjacent to and between the first set of bit lines, and allowing the voltage level of the bit line to rise in accordance with the boosting voltage applied to the second set of bit lines.

91. The non-volatile memory system of claim 90, wherein the voltage level of the bit line rises in relation to the boosting voltage and a level of capacitively coupling existing between the first set of bit lines and the second set of bit lines.

92. A non-volatile memory system, comprising:

a group of non-volatile storage elements having a channel region;

a bit line associated with the group of storage elements;

managing circuitry in communication with the group of storage elements and the bit line the programs a selected storage element of the group by source side injection that includes sensing a threshold voltage of the selected storage element, charging the bit line based on the threshold voltage of the selected memory cell, boosting a voltage of the bit line after charging, and transferring at least a portion of the voltage of the bit line into the channel region of the group of storage elements to program the selected storage element.

93. The non-volatile memory system of claim 92, wherein the managing circuitry senses an analog threshold voltage of the selected storage element.

94. The non-volatile memory system of claim 93, wherein the managing circuitry senses an analog threshold voltage by drain source reverse readout.

95. The non-volatile memory system of claim 94, wherein the managing circuitry senses the analog threshold voltage by drain source reverse readout by applying a first voltage to a source line for the group of storage elements, applying a pass voltage to unselected storage elements of the group, opening the group of storage elements to the bit line and the source line, and applying a target threshold voltage to the selected memory cell.

96. The non-volatile memory system of claim 95, wherein the managing circuitry charges the bit line by charging the bit line to the first voltage level when a difference between the target threshold voltage and an actual threshold voltage of the selected storage element is greater than the first voltage level, and charging the bit line to a level of the difference between the target threshold voltage and the actual threshold voltage when the difference is less than the first voltage level.

97. The non-volatile memory system of claim 92, wherein the managing circuitry includes a state machine.

98. The non-volatile memory system of claim 97, wherein the managing circuitry further includes column control circuitry and row control circuitry.