System and Method for Operating a Semiconductor Memory

• US 20090086554A1
• Filed: 09/28/2007
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Chanussot, Christophe, Gouin, Vincent
• Application Number:
  US11/864,109
• Publication Number:
  US 20090086554A1
• Time in Patent Office: Days
• US Class Current: 365/189.90
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A method for operating a semiconductor memory cell is disclosed. A first voltage is applied to the memory cell. The first voltage is dependent on temperature and semiconductor process variation in a manner that keeps the memory cell in a stable region of operation.

Claims

1. A method for operating a semiconductor memory cell, the method comprising applying a first voltage to the memory cell, wherein the first voltage comprises dependencies on semiconductor process variation and on temperature, and wherein the dependencies keep the memory cell in a stable region of operation.

2. The method of claim 1, wherein the applying the first voltage comprises

asserting the first voltage on a word line of the memory cell while the memory cell is being read;

and

asserting the first voltage on the word line of the memory cell while the memory cell is being written.

3. The method of claim 2, wherein:

the asserting the first voltage on the word line of the memory cell while the memory cell is being read comprises asserting the first voltage on the word line for a first duration; and

the asserting the first voltage on the word line of the memory cell while the memory cell is being written comprises asserting the first voltage on the word line for a second duration, wherein the first duration is greater than the second duration.

4. The method of claim 2, wherein:

the asserting the first voltage on the word line of the memory cell while the memory cell is being read comprises asserting the first voltage on the word line for a first duration; and

the asserting the first voltage on the word line of the memory cell while the memory cell is being written comprises asserting the first voltage on the word line for a second duration, wherein the first duration is less than the second duration.

5. The method of claim 1, further comprising:

applying a second voltage to the memory cell, the second voltage being greater than or equal to the first voltage, wherein;

applying the second voltage comprises asserting the second voltage on a word line of the memory cell while the memory cell is being written; and

applying the first voltage comprises asserting the first voltage on the word line of the memory cell while the memory cell is being read.

6. The method of claim 4, wherein the second voltage comprises a supply voltage

7. The method of claim 1, further comprising:

applying a second voltage to the memory cell, the second voltage being greater than or equal to the first voltage, wherein;

applying the second voltage comprises asserting the second voltage on a word line of the memory cell while the memory cell is being read; and

applying the first voltage comprises asserting the first voltage on the word line of the memory cell while the memory cell is being written.

8. The method of claim 7, wherein the second voltage comprises a supply voltage.

9. The method of claim 1, wherein the first voltage is proportional to a MOS threshold voltage, a diode junction voltage, or a bipolar junction transistor base-emitter voltage.

10. The method of claim 9, wherein the first voltage is inversely proportional to temperature.

11. The method of claim 1, wherein the dependencies maintain stability margins in fast conditions, and wherein the dependencies maintain read/write margins in slow conditions, and wherein the fast conditions comprise low thresholds and high temperatures and the slow conditions comprise high thresholds and low temperatures.

12. The method of claim 1, wherein the memory cell comprises a six transistor memory cell.

13. A method of operating a semiconductor memory cell, the method comprising reading the memory cell, the reading comprising applying a compensated voltage to a word line of the memory cell, the compensated voltage being less than or equal to a reference voltage, wherein the compensated voltage is proportional to a MOS threshold voltage.

14. The method of claim 13, further comprising writing the memory cell, the writing comprising applying the compensated voltage to the word line of the memory cell.

15. The method of claim 13, wherein the applying the compensated voltage comprises driving the word line with a word line driver, the word line driver comprising:

a compensation voltage generator comprising a compensation voltage output; and

a driver circuit coupled to the compensation voltage output and the word line.

16. The method of claim 15, wherein:

the compensation voltage generator comprises at least one diode-connected MOS transistor and a current supply coupled to the at least one diode-connected MOS transistor;

the current supply and the at least one diode-connected MOS transistor are coupled to the compensation voltage output; and

the at least one diode-connected MOS transistor comprises a MOS transistor comprising a gate and a drain, wherein the gate is electrically coupled to the drain.

17. The method of claim 16, wherein the at least one diode-connected MOS transistor comprises a plurality of MOS transistors coupled in series.

18. The method of claim 16, wherein the current supply comprises a transistor.

19. The method of claim 16, wherein the at least one diode-connected MOS transistor comprises an NMOS transistor and the current supply comprises a PMOS transistor.

20. A memory system comprising:

a memory cell coupled to a word line;

a voltage reference comprising at least one diode-connected MOS transistor, the at least one diode-connected MOS transistor comprising a gate and a drain, wherein the gate is electrically coupled to the drain; and

a word line driver coupled to the voltage reference, the word line driver comprising an output coupled to the word line.

21. The system of claim 20, wherein the at least one diode-connected MOS transistor comprises a plurality of diode-connected MOS transistors coupled in series.

22. The system of claim 20, wherein the voltage reference is coupled to a supply reference of the word line driver.

23. The system of claim 22, wherein the word line driver comprises a MOS transistor coupled between the voltage reference and the word line.

24. The system of claim 20, wherein the voltage reference further comprises a current source coupled to the at least one diode-connected MOS transistor.

25. The system of claim 24, wherein the current source comprises a MOS transistor.

26. The system of claim 20, further comprising a plurality of memory cells and a plurality of word line drivers, wherein a single voltage reference is coupled to supply references of the plurality of word line drivers.

27. The system of claim 20, wherein the voltage reference comprises a MOS switch coupled in series with the at least one diode-connected MOS transistor.

28. The system of claim 20, wherein the voltage reference is coupled to the output of the word line driver.