VOLTAGE SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY

• US 20090086555A1
• Filed: 10/30/2008
• Published: 04/02/2009
• Est. Priority Date: 06/27/2005
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: TAKEUCHI, Atsushi
• Granted Patent: US 7,821,863 B2
• Time in Patent Office: Days
• US Class Current: 365/189.90
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of an output signal of the first differential amplifier, and connects the output node to a low power supply line in response to the activation of an output signal of the second differential amplifier. Only during the activation period of the drivability control signal, a second driving circuit connects the output node to the high power supply line in response to the activation of the output signal of the first differential amplifier, and connects the output node to the low power supply line in response to the activation of the output signal of the second differential amplifier.

Claims

1. A method of generating a voltage at an output node, comprising:

activating a first driving circuit, in a first mode and a second mode, to supply a high voltage to the output node when the voltage is lower than a first voltage and to supply a low voltage to the output node when the voltage is higher than a second voltage; and

activating a second driving circuit, in the second mode, to supply the high voltage to the output node when the voltage is lower than the first voltage and to supply the low voltage to the output node when the voltage is higher than the second voltage.

2. The method according to claim 1, wherein the first mode is a stand-by state of a circuit to which the voltage is supplied, and the second mode is an active state of the circuit.

3. The method according to claim 1, further comprising:

comparing the voltage with the first voltage to generate a first comparison result;

comparing the voltage with the second voltage to generate a second comparison result; and

activating the first driving circuit based on the first comparison result or the second comparison result in the first mode and the second mode.

4. The method according to claim 1, wherein the second driving circuit is activated based on an active signal which indicates one of the first mode and the second mode.

5. The method according to claim 1, further comprising:

supplying the voltage to a pre-charge circuit.

6. The method according to claim 1, wherein the second voltage is higher than the first voltage.

7. The method according to claim 1, wherein the second driving circuit is not activated in the first mode.

8. A method of generating a voltage at output node to supply the voltage to a circuit, comprising:

supplying a high voltage to an output node via a first path when detecting that the voltage is lower than a first voltage;

supplying a low voltage to the output node via a second path when detecting that the voltage is higher than a second voltage;

supplying the high voltage to the output node via a third path, which is different from the first path, when detecting that the voltage is lower than a first voltage; and

supplying the low voltage to the output node via the fourth path, which is different from the third path, when detecting that the voltage is higher than a second voltage,

wherein the first path and the second path are used in a first mode and a second mode,

wherein the third mode and the fourth mode are used in the second mode.

9. The method according to claim 8, wherein the first mode is a stand-by state of the circuit and the second mode is an activate state of the circuit.

10. The method according to claim 8, wherein the first path is from a high voltage supply line to the output node via a first circuit,

wherein the second path is from a low voltage supply line to the output node via a second circuit.

11. The method according to claim 8, wherein the second voltage is higher than the first voltage.

12. The method according to claim 8, wherein the third path and the fourth path are not used in the first mode.