Method And System For Utilizing A Single PLL To Clock An Array Of DDFS For Multi-Protocol Applications

• US 20090086738A1
• Filed: 09/28/2007
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza
• Granted Patent: US 8,014,422 B2
• Time in Patent Office: Days
• US Class Current: 370/395.500
• CPC Class Codes: H04B 2001/0491 with frequency synthesizers, frequency converters or modulators
• CPC Class Codes: H04L 2027/0016 Stabilisation of local oscillators
• CPC Class Codes: H04L 2027/0036 using a recovered symbol clock
• CPC Class Codes: H04L 2027/0053 Closed loops
• CPC Class Codes: H04L 2027/0069 Loop filters
• CPC Class Codes: H04L 27/0014 Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657

Abstract

Methods and systems for utilizing a single PLL to clock an array of DDFS for multi-protocol applications are disclosed. Aspects of one method may include generating a first signal for use in generating a plurality of local oscillator (LO) signals. The first signal may be communicated to a plurality of LO generators. Each of the LO signals may be generated independently of each other by a corresponding one of the LO generators. Each of the LO signals may be communicated to one or more mixers, where each mixer may perform down-conversion or up-conversion. A LO generator may utilize, for example, a DDFS or a digital delay circuit. A frequency of a LO signal may be varied by adjusting a divide factor for a divider that generates a reference clock for the DDFS or for a divider that generates a second signal used for mixing with a signal generated by the DDFS. The LO signal frequency may also be varied by adjusting frequency control words received by a DDFS.

Claims

1. A method for processing signals, the method comprising:

generating a first signal; and

generating a plurality of local oscillator signals from said generated first signal, wherein each of said plurality of local oscillator signals are generated independently of each other via corresponding circuitry that comprises one of a direct digital frequency synthesizer (DDFS) or a digital delay circuit.

2. The method according to claim 1, comprising generating said first signal utilizing a phase locked loop circuit.

3. The method according to claim 1, comprising communicating one or more of said local oscillator signals to one or more mixers, wherein each mixer performs one of:

down-conversion of received signals and up-conversion of signals to be transmitted.

4. The method according to claim 1, comprising varying a frequency of a local oscillator signal by adjusting a divide factor for a divider that generates a reference clock for said DDFS.

5. The method according to claim 1, comprising varying a frequency of a local oscillator signal by adjusting a divide factor for a divider that generates a second signal that is used for mixing with a signal generated by said DDFS.

6. The method according to claim 1, comprising varying a frequency of a local oscillator signal by adjusting one or more frequency control words to be received by said DDFS in a corresponding one of said plurality of local oscillator generators.

7. The method according to claim 1, comprising delaying a phase of said first signal via said digital delay circuit to generate a second signal that is substantially 90°

out of phase with said first signal.

8. A machine-readable storage having stored thereon, a computer program having at least one code section for processing signals, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

generating a first signal; and

generating a plurality of local oscillator signals from said generated first signal, wherein each of said plurality of local oscillator signals are generated independently of each other via corresponding circuitry that comprises one of a direct digital frequency synthesizer (DDFS) or a digital delay circuit.

9. The machine-readable storage according to claim 8, wherein the at least one code section comprises code that enables generation of said first signal utilizing a phase locked loop circuit.

10. The machine-readable storage according to claim 8, wherein the at least one code section comprises code that enables communication of one or more of said local oscillator signals to one or more mixers, wherein each mixer performs one of:

down-conversion of received signals and up-conversion of signals to be transmitted.

11. The machine-readable storage according to claim 8, wherein the at least one code section comprises code that enables varying a frequency of a local oscillator signal by adjusting a divide factor for a divider that generates a reference clock for said DDFS.

12. The machine-readable storage according to claim 8, wherein the at least one code section comprises code that enables varying a frequency of a local oscillator signal by adjusting a divide factor for a divider that generates a second signal that is used for mixing with a signal generated by said DDFS.

13. The machine-readable storage according to claim 8, wherein the at least one code section comprises code that enables varying a frequency of a local oscillator signal by adjusting one or more frequency control words to be received by said DDFS in a corresponding one of said plurality of local oscillator generators.

14. The machine-readable storage according to claim 8, wherein the at least one code section comprises code that enables delaying of a phase of said first signal via said digital delay circuit to generate a second signal that is substantially 90°

out of phase with said first signal.

15. A system for processing signals, the system comprising:

one or more circuits that enable generation of a first signal; and

said one or more circuits comprise a plurality of local oscillator generators, and said one or more circuits enable generation of a plurality of local oscillator signals from said generated first signal, wherein each of said plurality of local oscillator signals are generated independently of each other via a corresponding one of said plurality of local oscillator generators that comprises one of a direct digital frequency synthesizer or a digital delay circuit.

16. The system according to claim 15, wherein said one or more circuits comprise a phase locked loop circuit that enables generation of said first signal.

17. The system according to claim 15, wherein said one or more circuits enable communication of one or more of said local oscillator signals to one or more mixers, where each mixer performs one of:

down-conversion of received signals and up-conversion of signals to be transmitted.

18. The system according to claim 15, wherein said one or more circuits comprise one or more processors that enable adjusting a divide factor for a divider that generates a reference clock for said DDFS, for varying a frequency of a local oscillator signal.

19. The system according to claim 15, wherein said one or more circuits comprise one or more processors that enable adjusting a divide factor for a divider that generates a second signal that is used for mixing with a signal generated by said DDFS, for varying a frequency of a local oscillator signal.

20. The system according to claim 15, wherein said one or more circuits comprise one or more processors that enable adjusting of one or more frequency control words to be received by said DDFS in a corresponding one of said plurality of local oscillator generators, for varying a frequency of a local oscillator signal.

21. The system according to claim 15, wherein said one or more circuits that comprises said digital delay circuit enable varying of a phase of said first signal to generate a second signal that is substantially 90°

out of phase with said first signal.