SEMICONDUCTOR LASER DIODE WITH REDUCED PARASITIC CAPACITANCE

• US 20090086779A1
• Filed: 09/25/2008
• Published: 04/02/2009
• Est. Priority Date: 09/27/2007
• Status: Abandoned Application

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Matsumura, Atsushi
• Application Number:
  US12/237,867
• Publication Number:
  US 20090086779A1
• Time in Patent Office: Days
• US Class Current: 372/45.10
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10155 being other than a cuboid
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/0234 Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
• CPC Class Codes: H01S 5/0237 by soldering
• CPC Class Codes: H01S 5/0422 with n- and p-contacts on the same side of the active layer
• CPC Class Codes: H01S 5/06226 Modulation at ultra-high frequencies
• CPC Class Codes: H01S 5/2224 semi-insulating semiconductors
• CPC Class Codes: H01S 5/2231 with inner confining structure only between the active layer and the upper electrode
• CPC Class Codes: H01S 5/3095 Tunnel junction
• CPC Class Codes: H01S 5/34373 based on InGa(Al)AsP

Abstract

The LD of the invention provides a semiconductor stack including the current confinement region with the active mesa and the semi-insulating burying regions putting the active mesa therebeteen and the conductive region in contiguity with the current confinement region. The current confinement region and the conductive region are provided on epitaxially grown cladding layer. Two semiconductor regions, which are physically isolated to each other and each includes the semiconductor substrate, are provided on the semiconductor stack. One of regions comes in contact with one of burying regions and the active mesa, while, the other semiconductor regions comes in contact with the other of burying regions and the conductive region.

Claims

1. A semiconductor laser diode mounted on a sub-mount, comprising:

a first cladding layer coming in contact with said sub-mount;

a current confinement region provided on said first cladding layer, said current confinement region including an active mesa and first and second burying regions provided in both sides of said active mesa;

a conductive region provided in contiguity with said current confinement region on said first cladding layer and;

a first semiconductor region with a first electrode on a top surface thereof, said first semiconductor region being provided on said active mesa and said first burying region; and

a second semiconductor region with a second electrode on a top surface thereof, said second semiconductor region being provide on said second burying region and said conductive region,

wherein said first and second semiconductor regions are physically isolated to each other, and

wherein said first and second burying regions are semi-insulating characteristic.

2. The laser diode according to claim 1,

wherein said active mesa includes an active layer and a tunnel junction, and

wherein said first and second semiconductor substrates, said conductive region, and said first and second semiconductor regions have a same conducting type.

3. The laser diode according to claim 1,

wherein said first semiconductor region includes a second cladding layer and a first semiconductor substrate, said second cladding layer being provided on said first burying region and said active mesa, said first semiconductor substrate being provided on said second cladding layer and providing said first electrode thereon.

4. The laser diode according to claim 3,

wherein said second semiconductor region includes a third cladding layer and a second semiconductor substrate, said third cladding layer being provided on said second burying region and said conductive region, said second semiconductor substrate being provided on said third cladding layer and providing said second electrode thereon.

5. The laser diode according to claim 4,

wherein said second cladding layer and said third cladding layer have substantially same thickness and same doping concentration.

6. The laser diode according to claim 1,

wherein said first and second semiconductor regions are physically isolated to each other by a groove reaching a top surface of said second burying region.

7. The laser diode according to claim 1,

wherein said laser diode is mounted on said sub-mount through a metal film.

8. A method to produce an assembly of a semiconductor laser diode on a sub-mount, comprising steps of:

growing a stack of semiconductor layers epitaxially on a semiconductor substrate, said semiconductor layers including an active layer;

etching said stack to form an active mesa including said active layer;

burying said active mesa by selectively growing a semi-insulating semiconductor layer on both sides of said active mesa to form a current confinement structure;

forming a conductive region by etching a portion of said burying layer and burying said portion with said conductive region; and

etching a portion of said substrate to expose a surface of said burying region to form a pair of semiconductor regions physically isolated to each other.

9. The method according to claim 8,

wherein said step to grow said stack includes processes to grow a cladding layer, a tunnel junction, a separated confinement hetero-structure layer, said active layer, another separated and confinement hetero-structure layer.

10. The method according to claim 9,

further comprising a step, after etching said portion of said substrate, to mount said stack of said semiconductor layers on said sub-mount such that said cladding layer faces and comes in contact with said sub-mount.