Equalization And Decision-Directed Loops With Trellis Demodulation In High Definition TV

• US 20090086808A1
• Filed: 12/08/2008
• Published: 04/02/2009
• Est. Priority Date: 11/03/1998
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Tan, Loke Kun, Jaffe, Steven T., Liu, Tian-Min
• Granted Patent: US 8,098,725 B2
• Time in Patent Office: Days
• US Class Current: 375/233
• CPC Class Codes: H04B 1/68 for wholly or partially suppressing the carrier or one side band
• CPC Class Codes: H04L 2025/03382 Single of vestigal sideband
• CPC Class Codes: H04L 2025/0342 QAM
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2027/0032 at baseband and passband
• CPC Class Codes: H04L 2027/0042 the equaliser providing the offset correction per se
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 2027/0087 Out-of-band signals, (e.g. pilots)
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/066 Carrier recovery circuits H04L27/2271 takes precedence
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 27/3427 in which the constellation is the n - fold Cartesian product of a single underlying two-dimensional constellation
• CPC Class Codes: H04L 27/3827 in which the carrier is recovered using only the demodulated baseband signals
• CPC Class Codes: H04N 11/24 High-definition television systems
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
• CPC Class Codes: H04N 5/211 Ghost signal cancellation H04N23/81 takes precedence
• CPC Class Codes: H04N 5/44 : Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27

Abstract

Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE'"'"'s ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

Claims

1. A decision directed equalization circuit, comprising:

a Trellis coded modulation (TCM) decoder to provide a maximum likelihood decision based on a current symbol; and

a DFE to process the maximum likelihood decision with one or more first equalization coefficients to provide a weighted maximum likelihood decision; and

a first summing junction to combine the weighted maximum likelihood decision and one or more symbol samples to provide the current symbol.

2. The decision directed equalization circuit of claim 1, wherein the TCM decoder determines a maximum likelihood sequence path, and wherein the TCM decoder provides the maximum likelihood decision based upon the maximum likelihood sequence path.

3. The decision directed equalization circuit of claim 2, wherein the TCM decoder determines correlations between the current symbol and one or more intermediate maximum likelihood decisions to determine the maximum likelihood sequence path.

4. The decision directed equalization circuit of claim 3, wherein the TCM decoder determines correlations between the current symbol and the one or more intermediate maximum likelihood decisions by maximum likelihood sequence estimation.

5. The decision directed equalization circuit of claim 1, wherein the maximum likelihood decision includes one symbol from at least one of a current maximum likelihood decision and one or more intermediate maximum likelihood decisions.

6. The decision directed equalization circuit of claim 5, wherein the DFE processes the one symbol from the at least one of the current maximum likelihood decision and the one or more intermediate maximum likelihood decisions with the one or more first equalization coefficients.

7. The decision directed equalization circuit of claim 1, wherein the maximum likelihood decision includes more than one symbol from at least one of a current maximum likelihood decision and one or more intermediate maximum likelihood decisions.

8. The decision directed equalization circuit of claim 7, wherein the DFE processes the more than one symbol from the at least one of the current maximum likelihood decision and the one or more intermediate maximum likelihood decisions with the one or more first equalization coefficients.

9. The decision directed equalization circuit of claim 1, further comprising:

a first delay circuit configured to delay the current symbol by a first delay; and

a symbol timing reference loop to provide a symbol timing reference based on an output of the first delay circuit and the maximum likelihood decision,

wherein the first delay causes an output of the first delay circuit to have a substantially similar time stamp as the maximum likelihood decision.

10. The decision directed equalization circuit of claim 1, further comprising:

a second delay circuit configured to delay the current symbol by a second delay; and

a carrier loop configured to estimate at least one of;

an angle of an output of the second delay circuit and a phase of the output of the second delay circuit based on the maximum likelihood decision,

wherein the second delay causes the output of the second delay circuit to have a substantially similar time stamp as the maximum likelihood decision.

11. The decision directed equalization circuit of claim 1, further comprising:

a feedword equalizer (FFE) to process an input signal with one or more second equalization coefficients to provide the one or more symbol samples.

12. The decision directed equalization circuit of claim 11, further comprising:

a third delay circuit configured to delay the current symbol by a third delay; and

a second summing junction configured to combine an output of the third delay circuit and the maximum likelihood decision to produce an error term,

wherein the third delay causes the output of the third delay circuit to have a substantially similar time stamp as the maximum likelihood decision.

13. The decision directed equalization circuit of claim 12, wherein the error term is used to drive at least one of:

a coefficient tap update of the FFE; and

a coefficient tap update of the DFE.

14. The decision directed equalization circuit of claim 1, wherein the TCM decoder comprises:

a decision device configured to calculate a path metric for one or more states of the current symbol;

a path metrics module to produce a selection signal based on the path metric;

a path memory module including one or more traceback registers, wherein each traceback register corresponds to a respective one of the one or more states; and

a multiplexer to select one of the one or more traceback registers based on the selection signal to provide the maximum likelihood decision,

wherein at least one of the path memory module and the path metrics module includes one or more intermediate likelihood decisions.

15. The decision directed equalization circuit of claim 14, wherein the path metric represents a distance between each of the one or more states and the current symbol.

16. A method, comprising:

(a) providing a maximum likelihood decision based on a current symbol; and

(b) processing the maximum likelihood decision with one or more first equalization coefficients to provide a weighted maximum likelihood decision; and

(c) combining the weighted maximum likelihood decision and one or more symbol samples to provide the current symbol.

17. The method of claim 16, wherein step (a) comprises:

(a)(i) determining a maximum likelihood sequence path

(a)(ii) providing the maximum likelihood decision based upon the maximum likelihood sequence path.

18. The method of claim 17, wherein step (a)(i) comprises:

(a)(i)(A) determining correlations between the current symbol and one or more intermediate maximum likelihood decisions to determine the maximum likelihood sequence path.

19. The method of claim 18, wherein step (a)(i)(A) comprises:

(a)(i)(A)(1) determining correlations between the current symbol and the one or more intermediate maximum likelihood decisions by maximum likelihood sequence estimation.

20. The method of claim 16, wherein step (a) comprises:

(a)(i) providing one symbol from at least one of a current maximum likelihood decision and one or more intermediate maximum likelihood decisions based on the current symbol.

21. The method of claim 20, wherein step (b) comprises:

(b)(i) processing the one symbol from at least one of the current maximum likelihood decision and the one or more intermediate maximum likelihood decisions with the one or more first equalization coefficients to provide the weighted maximum likelihood decision.

22. The method of claim 16, wherein step (a) comprises:

(a)(i) providing more than one symbol from at least one of a current maximum likelihood decision and one or more intermediate maximum likelihood decisions based on the current symbol.

23. The method of claim 22, wherein step (b) comprises:

(b)(i) processing the more than one symbol from at least one of the current maximum likelihood decision and the one or more intermediate maximum likelihood decisions with the one or more first equalization coefficients to provide the weighted maximum likelihood decision.

24. The method of claim 16, further comprising:

(d) delaying the current symbol by a first delay to provide a first delayed symbol, wherein the first delay causes the first delayed symbol to have a substantially similar time stamp as the maximum likelihood decision; and

(e) providing a symbol timing reference based on the first delayed symbol and the maximum likelihood decision.

25. The method of claim 16, further comprising:

(d) delaying the current symbol by a second delay to provide a second delayed symbol, wherein the second delay causes the second delayed symbol to have a substantially similar time stamp as the maximum likelihood decision; and

(e) estimating at least one of;

an angle of the second delayed symbol and a phase of the output of the second delayed symbol based on the maximum likelihood decision.

26. The method of claim 16, further comprising:

(d) processing an input signal with one or more second equalization coefficients to provide the one or more symbol samples.

27. The method of claim 26, further comprising:

(e) delaying the current symbol by a third delay to provide a third delayed symbol, wherein the third delay causes the third delayed symbol to have a substantially similar time stamp as the maximum likelihood decision; and

(f) combining the third delayed symbol and the maximum likelihood decision to produce an error term.

28. The method of claim 27, further comprising:

(g) driving a coefficient tap update using the error term.

29. The method of claim 16, wherein step (a) comprises:

(a)(i) calculating a path metric for one or more states of the current symbol;

(a)(ii) producing a selection signal based on the path metric;

(a)(iii) select a respective one of the one or more states based on the selection signal to provide the maximum likelihood decision.

30. The method of claim 29, wherein step (a)(i) comprises:

(a)(i)(A) determining a distance between each of the one or more states and the current symbol.