METHOD TO IMPROVE ELECTRICAL LEAKAGE PERFORMANCE AND TO MINIMIZE ELECTROMIGRATION IN SEMICONDUCTOR DEVICES

• US 20090087577A1
• Filed: 09/27/2007
• Published: 04/02/2009
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: TEL Manufacturing and Engineering of America, Inc.
• Original Assignee: TEL Epion Inc. (Tokyo Electron Limited)
• Inventors: Hautala, John J., Russell, Noel, Sherman, Steven
• Granted Patent: US 7,981,483 B2
• Time in Patent Office: Days
• US Class Current: 427/523
• CPC Class Codes: H01J 2237/0812 Ionized cluster beam [ICB] sources
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288

Abstract

Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices are generally described herein. Other embodiments may be described and claimed.

Claims

1. A method of minimizing electromigration in conductive paths and gettering metal contaminants in dielectric regions of a workpiece, the method comprising:

planarizing a top surface of a workpiece to form a substantially planar surface with a plurality of conductive paths and a plurality of dielectric regions;

exposing the top surface of the workpiece to a phosphorous source to form a phosphorous-doped layer in the plurality of conductive paths and the plurality of dielectric regions; and

forming a barrier layer over the phosphorous-doped layer.

2. The method of claim 1, further including a pre-treatment step prior to exposing the top surface of the workpiece to a phosphorous source.

3. The method of claim 1, wherein the phosphorous source is delivered by a system selected from the group consisting of a thermal treatment system, a plasma treatment system, an ion implantation system, and a gas cluster ion beam system.

4. The method of claim 1, wherein the phosphorous-doped layer comprises between 0.1 atomic % and 10 atomic % phosphorus.

5. The method of claim 1, wherein the depth of the phosphorous-doped layer is between 50 and 200 angstroms.

6. The method of claim 1, wherein the substantially planar surface is planarized by a chemical mechanical planarization or an electropolishing process.

7. The method of claim 1, wherein the phosphorous-doped layer has a peak phosphorus concentration depth in the plurality of dielectric regions, the peak phosphorus concentration depth is between 100 and 500 angstroms below the top surface.

8. The method of claim 1, wherein the phosphorus source comprises phosphine and a non-condensable source gas selected from the group consisting of helium, neon, and hydrogen.

9. The method of claim 8, further including a second condensable gas source selected from the group consisting of argon, nitrogen, carbon dioxide, and oxygen.

10. The method of claim 1, wherein the barrier layer is selected from the group consisting of silicon nitride, silicon carbide, nitrogen doped silicon carbide, boron carbon nitride, and boron nitride.

11. A method of forming a phosphorus-doped layer, the method comprising:

planarizing a top surface of a workpiece to form a substantially planar surface with a plurality of conductive paths and a plurality of dielectric regions;

infusing phosphorus into the top surface of the workpiece to form a phosphorous-doped layer in the plurality of conductive paths and the plurality of dielectric regions; and

forming a barrier layer over the phosphorous-doped layer.

12. The method of claim 11, further including a pre-treatment step prior to infusing phosphorus into the top surface of the workpiece.

13. The method of claim 11, wherein the phosphorous is delivered by a gas cluster ion beam system.

14. The method of claim 11, wherein the phosphorous-doped layer comprises between 0.1 atomic % and 10 atomic % phosphorus.

15. The method of claim 11, wherein a maximum depth of the phosphorous-doped layer is about 50 angstroms.

16. The method of claim 11, wherein the substantially planar surface is planarized by a chemical mechanical planarization or an electropolishing process.

17. The method of claim 11, wherein a phosphorus source comprising phosphine and a non-condensable gas is used to infuse phosphorus into the top surface of the workpiece.

18. The method of claim 17, wherein the non-condensable gas is selected from the group consisting of helium, neon, and hydrogen.

19. The method of claim 17, further including a second condensable gas source selected from the group consisting of argon, nitrogen, carbon dioxide, and oxygen.

20. The method of claim 11, wherein the barrier layer is selected from the group consisting of silicon nitride, silicon carbide, nitrogen doped silicon carbide, boron carbon nitride, and boron nitride.