METHOD FOR FABRICATING RECESS GATE IN SEMICONDUCTOR DEVICE

• US 20090087960A1
• Filed: 09/26/2008
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: CHO, Yong-Tae, Kim, Eun-Mi
• Granted Patent: US 7,838,361 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.

Claims

1. A method for fabricating a recess gate in a semiconductor device, the method comprising:

etching a silicon substrate to form a trench that defines an active region;

forming a device isolation layer that gap-fills the trench;

forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region; and

forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier,

wherein the second etching is performed after removing the amorphous carbon layer.

2. The method of claim 1, further comprising, after the second etching, third etching in situ to increase a width of the recess region.

3. The method of claim 1, wherein forming the recess region comprises:

performing the first etching using the amorphous carbon layer as an etch barrier to form a first recess region;

removing the amorphous carbon layer; and

performing the second etching using the oxide layer as an etch barrier to form a second recess region that is wider than the first recess region.

4. The method of claim 3, wherein the first etching, the removing of the amorphous carbon layer, and the second etching are performed in situ in a plasma etching apparatus.

5. The method of claim 4, wherein the first etching and the second etching are performed using a mixture of chlorine-based gas and bromine-based gas.

6. The method of claim 5, wherein the first etching and the second etching are performed at an HBr-to-Cl₂ flow rate ratio of approximately 5:

1, by applying a pressure of approximately 5 mtorr to approximately 20 mtorr, a source power of approximately 500 W to approximately 1500 W, and a bias power of approximately 100 V to approximately 300 V.

7. The method of claim 4, wherein the removing of the amorphous carbon layer is performed using an O₂ plasma with a flow rate of approximately 200 sccm to approximately 1000 sccm and by applying a source power without applying a bias power.

8. The method of claim 2, wherein the third etching is performed by adding a mixture of fluorine-based gas and oxygen gas to a mixture of chlorine-based gas and bromine-based gas.

9. The method of claim 8, wherein the fluorine-based gas comprises one of sulfur fluoride gas, nitrogen fluoride gas, and carbon fluoride gas.

10. The method of claim 8, wherein the third etching is performed by applying a pressure of approximately 20 mtorr to approximately 100 mtorr, a source power of approximately 500 W to approximately 1500 W, and a bias power of approximately 50 W or less.

11. The method of claim 8, wherein the bromine-based gas is HBr and the chorine-based gas is Cl₂.

12. The method of claim 4, wherein the plasma etching apparatus uses one of Magnetically Enhanced Reactive Ion Etching (MERIE), Transformer Coupled Plasma (TCP), Inductively Coupled Plasma (ICP), Microwave Down Stream (MDS), Electron Cyclotron Resonance (ECR), and Helical as a plasma source.

13. A method for forming a recess channel in a semiconductor device, the method comprising:

forming a hard mask layer over a semiconductor substrate, the hard mask layer comprising a stack of a passivation layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the semiconductor substrate;

etching the channel target region using the amorphous carbon layer as an etch barrier to form a first recess region;

removing the amorphous carbon layer; and

etching a bottom of the first recess region using the passivation layer as an etch barrier to form a second recess region.

14. The method of claim 13, wherein the etching the channel target region, the removing of the amorphous carbon layer, and the etching the bottom of the first recess region are performed in situ in a plasma etching apparatus.

15. The method of claim 14, wherein the etching the channel target region and the etching the bottom of the first recess region are performed using the same etch gas, the same pressure, the same source power, and the same bias power.

16. The method of claim 14, wherein the removing of the amorphous carbon layer is performed using an O₂ plasma and by applying a source power without applying a bias power.

17. The method of claim 14, wherein the plasma etching apparatus uses one of Magnetically Enhanced Reactive Ion Etching (MERIE), Transformer Coupled Plasma (TCP), Inductively Coupled Plasma (ICP), Microwave Down Stream (MDS), Electron Cyclotron Resonance (ECR), and Helical as a plasma source.

18. The method of claim 13, wherein the semiconductor substrate comprises a silicon substrate and the passivation layer comprises an oxide layer.

19. The method of claim 13, further comprising, after etching the bottom of the first recess region, performing etching in situ to increase a width of the second recess region.

20. A method for fabricating a recess gate in a semiconductor device, the method comprising:

etching a silicon substrate to form a trench that defines an active region;

forming a device isolation layer in the trench;

forming a hard mask layer over the silicon substrate, the hard mask layer comprising an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region;

first etching the channel target region using the amorphous carbon layer as an etch barrier to form a first recess region;

removing the amorphous carbon layer;

second etching a bottom of the first recess region using the oxide layer as an etch barrier to form a second recess region, wherein the second recess region is wider than the first recess region.

21. The method of claim 20, further comprising third etching the recess region to widen the second recess region.

22. A method for forming a recess channel in a semiconductor device, the method comprising:

forming a hard mask layer over a semiconductor substrate, the hard mask layer comprising a passivation layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the semiconductor substrate;

etching the channel target region using the amorphous carbon layer as an etch barrier to form a first recess region;

removing the amorphous carbon layer; and

etching a bottom of the first recess region using the passivation layer as an etch barrier to form a second recess region, wherein the second recess region is wider than the first recess region.

23. The method of claim 22, further comprising etching sides of the second recess region to increase a width of the second recess region.