DUAL DAMASCENE WITH AMORPHOUS CARBON FOR 3D DEEP VIA/TRENCH APPLICATION

• US 20090087979A1
• Filed: 09/28/2007
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Konevecki, Michael W., Raghuram, Usha
• Granted Patent: US 8,298,931 B2
• Time in Patent Office: Days
• US Class Current: 438/620
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes

Abstract

A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 μm. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask.

Claims

1. A method for fabricating a 3-D monolithic memory device, comprising:

first patterning of a first insulating layer to form a trench therein using a first amorphous carbon hard mask;

applying amorphous carbon to fill in at least a portion of the trench and to provide an amorphous carbon layer above the first insulating layer;

second patterning of the first insulating layer, using a second amorphous carbon hard mask formed from the amorphous carbon layer, to form a via in the first insulating layer which is aligned with the trench and extends below the trench; and

providing a conductive material in the trench and via.

2. The method of claim 1, further comprising:

patterning the amorphous carbon layer using an anti-reflective coating as a hard mask to obtain the second amorphous carbon hard mask.

3. The method of claim 2, wherein:

the amorphous carbon layer is in contact with a top surface of the first insulating layer, and the anti-reflective coating is in contact with a top surface of the amorphous carbon layer.

4. The method of claim 1, further comprising:

applying a dielectric anti-reflective coating above the amorphous carbon layer, applying a bottom anti-reflective coating above the dielectric anti-reflective coating, and patterning the amorphous carbon layer using the dielectric anti-reflective coating and the bottom anti-reflective coating as hard masks to provide the second amorphous carbon hard mask.

5. The method of claim 1, wherein:

the via extends through multiple levels of the memory device.

6. The method of claim 1, wherein:

the trench extends laterally in a level of the memory device.

7. The method of claim 1, wherein:

the amorphous carbon layer is in contact with a top surface of the first insulating layer.

8. The method of claim 1, further comprising:

removing the first amorphous carbon hard mask prior to the applying amorphous carbon.

9. The method of claim 1, wherein:

a depth of the via is greater than 1 μ

m.

10. A method for fabricating a 3-D monolithic memory device, comprising:

first patterning of a first insulating layer to form a via therein using a first amorphous carbon hard mask;

applying amorphous carbon to fill in at least a portion of the via and to provide an amorphous carbon layer above the first insulating layer;

second patterning of the first insulating layer, using at least the amorphous carbon layer as a second amorphous carbon hard mask, to form a trench in the first insulating layer aligned with the via, the via extends below the trench; and

providing a conductive material in the trench and via.

11. The method of claim 10, further comprising:

patterning the amorphous carbon layer using an anti-reflective coating as a hard mask to obtain the second amorphous carbon hard mask.

12. The method of claim 11, wherein:

the amorphous carbon layer is in contact with a top surface of the first insulating layer, and the anti-reflective coating is in contact with a top surface of the amorphous carbon layer.

13. The method of claim 10, further comprising:

applying a dielectric anti-reflective coating above the amorphous carbon layer, applying a bottom anti-reflective coating above the dielectric anti-reflective coating, and patterning the amorphous carbon layer using the dielectric anti-reflective coating and the bottom anti-reflective coating as hard masks to provide the second amorphous carbon hard mask.

14. The method of claim 10, wherein:

the via extends through multiple levels of the memory device.

15. The method of claim 10, wherein:

the trench extends laterally in a level of the memory device.

16. The method of claim 10, wherein:

the amorphous carbon layer is in contact with a top surface of the first insulating layer.

17. The method of claim 10, further comprising:

removing the first amorphous carbon hard mask prior to the applying amorphous carbon.

18. The method of claim 10, wherein:

a depth of the via is greater than 1 μ

m.

19. A method for fabricating a 3-D monolithic memory device, comprising:

forming a vertical conductive interconnect which extends in multiple levels in the memory device, the vertical conductive interconnect comprises a via and trench which are formed by a dual damascene process in which at least one of the via and trench is patterned using an associated amorphous carbon hard mask, and a conductive material is provided in the via and trench.

20. The method of claim 19, wherein the dual damascene process comprises:

first patterning an insulating layer using the associated amorphous carbon hard mask to form the via or trench;

applying amorphous carbon to fill in at least a portion of the via and to provide an amorphous carbon layer above the insulating layer; and

second patterning of the insulating layer, using at least the amorphous carbon layer as an additional amorphous carbon hard mask, to form the trench or via in the insulating layer, the via extends below the associated trench, the second patterning forms the trench when the first patterning forms the via, and the second patterning forms the via when the first patterning forms the trench.

21. The method of claim 20, wherein the dual damascene process comprises:

removing the associated amorphous carbon hard mask after the first patterning and prior to the applying amorphous carbon.

22. The method of claim 20, wherein the dual damascene process comprises:

patterning the amorphous carbon layer using an anti-reflective coating as a hard mask to obtain the additional amorphous carbon hard mask.

23. The method of claim 22, wherein:

the amorphous carbon layer is in contact with a top surface of the insulating layer, and the anti-reflective coating is in contact with a top surface of the amorphous carbon layer.