Apparatus and Methods for Frequency Control in a Multi-Output Frequency Synthesizer
First Claim
1. A frequency synthesizer circuit, comprising:
- a first phase-locked loop circuit configured to generate a first output signal phase-locked to a reference clock signal;
a second phase-locked loop circuit configured to generate a second output signal phase-locked to the same reference clock signal; and
a frequency correction circuit configured to correct the first output signal by adjusting a first frequency-division ratio in the first phase-locked loop circuit and generating a control signal to adjust the frequency of the reference clock signal, in response to a detected frequency error in the first output signal.
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Abstract
Methods and circuits for synthesizing two or more signals phase-locked to a common reference frequency signal are disclosed. In one embodiment, a method comprises generating first and second output signals phase-locked to a reference clock signal, using first and second phase-locked loop circuits. In response to a detected frequency error in the first output signal, the first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit. The second output signal is corrected, separately from the correction to the first output signal, by adjusting a frequency-division ratio in the second phase-locked loop circuit, using an adjustment parameter calculated from the detected frequency error. In another exemplary method, first and second output signals are generated as described above, using first and second phase-locked loop circuits. The first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit and generating a control signal to adjust the frequency of the reference clock signal, in response to detected frequency error in the first output signal. Because the second output signal is derived from the common reference clock signal, adjustments to the reference clock frequency will also adjust the frequency of the second output signal. Additional adjustments to the second output signal may be applied in some embodiments by adjusting a frequency-division ratio in the second phase-locked loop circuits. Circuits for implementing the described methods are also disclosed.
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Citations
25 Claims
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1. A frequency synthesizer circuit, comprising:
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a first phase-locked loop circuit configured to generate a first output signal phase-locked to a reference clock signal; a second phase-locked loop circuit configured to generate a second output signal phase-locked to the same reference clock signal; and a frequency correction circuit configured to correct the first output signal by adjusting a first frequency-division ratio in the first phase-locked loop circuit and generating a control signal to adjust the frequency of the reference clock signal, in response to a detected frequency error in the first output signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A frequency synthesizer circuit, comprising:
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a first phase-locked loop circuit configured to generate a first output signal phase-locked to a reference clock signal; a second phase-locked loop circuit configured to generate a second output signal phase-locked to the same reference clock signal; and a frequency correction circuit configured to; correct the first output signal by adjusting a first frequency-division ratio in the first phase-locked loop circuit in response to a detected frequency error in the first output signal; calculate an adjustment parameter based on the detected frequency error; and correct the second output signal by adjusting a second frequency-division ratio in the second phase-locked loop circuit, using the adjustment parameter. - View Dependent Claims (10, 11, 12, 13)
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14. A method for synthesizing two or more output signals from a reference clock signal, comprising:
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generating a first output signal phase-locked to the reference clock signal, using a first phase-locked loop circuit; generating a second output signal phase-locked to the reference clock signal, using a second phase-locked loop circuit; correcting the first output signal by adjusting a first frequency-division ratio in the first phase-locked loop circuit and generating a control signal to adjust the frequency of the reference clock signal, in response to detected frequency error in the first output signal. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method for synthesizing two or more output signals from a reference clock signal, comprising:
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generating a first output signal phase-locked to the reference clock signal, using a first phase-locked loop circuit; generating a second output signal phase-locked to the reference clock signal, using a second phase-locked loop circuit; correcting the first output signal by adjusting a first frequency-division ratio in the first phase-locked loop circuit in response to detected frequency error in the first output signal; calculating an adjustment parameter based on the detected frequency error; and correcting the second output signal separately from the correction to the first output signal by adjusting a second frequency-division ratio in the second phase-locked loop circuit, using the adjustment parameter. - View Dependent Claims (21, 22)
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23. A communications device, comprising
a communications transceiver circuit; -
a second receiver circuit; a first phase-locked loop circuit configured to generate a first output signal phase-locked to a reference clock signal, for use by the communications transceiver; a second phase-locked loop circuit configured to generate a second output signal phase-locked to the same reference clock signal, for use by the second receiver circuit; and a frequency correction circuit configured to correct the first output signal by adjusting a first frequency-division ratio in the first phase-locked loop circuit and generating a control signal to adjust the frequency of the reference clock signal, in response to a frequency error in the first output signal detected by the communications transceiver circuit. - View Dependent Claims (24, 25)
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Specification