WIRELESS TRANSCEIVER AND WIRELESS TRANSMISSION METHOD

• US 20090088101A1
• Filed: 10/01/2008
• Published: 04/02/2009
• Est. Priority Date: 10/02/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Agawa, Kenichi
• Granted Patent: US 8,145,168 B2
• Time in Patent Office: Days
• US Class Current: 455/127.200
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving

Abstract

A DC offset of a VGA is measured by selecting a ground contact of a switch. Then, the gain of the VGA is set at an appropriate value, monitoring contacts of the switch are successively selected, and the output values of an ADC for the respective cases are measured with the input to a DAC set at zero. Then, the DC offset of the VGA is removed, the DC offset value of each circuit block, such as DAC, in a transmitting part is calculated, and parameters are set so that the DC offset value of each circuit block is minimized.

Claims

1. A wireless transceiver, comprising:

a receiving part that has an amplifying circuit that amplifies a received signal and an analog-to-digital converting circuit that converts the signal amplified by the amplifying circuit from analog to digital;

a transmitting part that has a plurality of circuit blocks having different functions for transmitting a signal by wireless;

a switch that performs switching among output signals of the circuit blocks forming the transmitting part for selective input thereof to the amplifying circuit;

a DC offset compensating part capable of compensating for a DC offset occurring in the amplifying circuit; and

a controlling circuit that performs control to cancel or reduce a DC offset occurring in each of the plurality of circuit blocks based on a digital signal output from the analog-to-digital converting circuit when the output signal of each of the plurality of circuit blocks forming the transmitting part is selectively input to the amplifying circuit.

2. The wireless transceiver according to claim 1, wherein the DC offset compensating part has an offset canceling part that holds a state where a DC offset occurring in the amplifying circuit (when a signal is input to the amplifying circuit) is cancelled.

3. The wireless transceiver according to claim 1, wherein the controlling circuit performs setting of a parameter for each of the plurality of circuit blocks forming the transmitting part so that the DC offset occurring in the circuit block is minimized and performs control of at least one circuit block.

4. The wireless transceiver according to claim 2, wherein the controlling circuit performs setting of a parameter for each of the plurality of circuit blocks forming the transmitting part so that the DC offset occurring in the circuit block is minimized and performs control of at least one circuit block.

5. The wireless transceiver according to claim 1, further comprising:

a compensating part that compensates for a mismatch that occurs between an I signal path and a Q signal path.

6. The wireless transceiver according to claim 2, further comprising:

a compensating part that compensates for a mismatch that occurs between an I signal path and a Q signal path.

7. The wireless transceiver according to claim 3, further comprising:

a compensating part that compensates for a mismatch that occurs between an I signal path and a Q signal path.

8. The wireless transceiver according to claim 4, further comprising:

a compensating part that compensates for a mismatch that occurs between an I signal path and a Q signal path.

10. The wireless transceiver according to claim 1, wherein the DC offset compensating part connects an input terminal of the amplifying circuit to the ground via the switch, performs setting of a gain of the amplifying circuit, fetches a digital value produced by analog-to-digital conversion by the analog-to-digital converting circuit for the set gain, measures and stores the digital value as a DC offset value, and compensates for the DC offset of the amplifying circuit in accordance with a gain actually used.

11. The wireless transceiver according to claim 10, wherein the DC offset compensating part connects the input terminal of the amplifying circuit to a signal source having no DC offset via the switch when the DC offset value of the amplifying circuit is measured.

12. The wireless transceiver according to claim 10, wherein the DC offset compensating part is capable of measuring the value of a small DC offset equal to or lower than the resolution of the analog-to-digital converting circuit by setting the gain of the amplifying circuit at a large value within a predetermined range when the gain of the amplifying circuit is set and the DC offset is measured.

13. The wireless transceiver according to claim 3, wherein the controlling circuit compensates for a residual DC offset of the transmitting part that is not cancelled by the DC offset minimization by the parameter setting, by using a compensation amount of a reverse polarity.

14. The wireless transceiver according to claim 4, wherein the controlling circuit compensates for a residual DC offset of the transmitting part that is not cancelled by the DC offset minimization by the parameter setting, by using a compensation amount of a reverse polarity.

15. The wireless transceiver according to claim 1, wherein, in a case where each of the plurality of circuit blocks forming the transmitting part is composed of a plurality of circuit elements that have different characteristics and are switchably used, the controlling circuit performs control to minimize the DC offset of the circuit block by performing control to switch among the circuit elements.

16. The wireless transceiver according to claim 2, wherein the DC offset compensating part has a digital DC offset canceling circuit, in which a value set for canceling the DC offset is a digital value, as the offset canceling part.

17. The wireless transceiver according to claim 2, wherein the DC offset compensating part has a digital-to-analog converting circuit as the offset canceling part, and the controlling circuit sets a digital value for DC offset canceling from a setting register provided therein into the digital-to-analog converting circuit.

18. The wireless transceiver according to claim 3, wherein the wireless transceiver has a digital-to-analog converting circuit that converts transmission data from the controlling circuit from digital to analog as one of the plurality of circuit blocks forming the transmitting part, and the controlling circuit supplies a compensation value for canceling a residual DC offset, that is not cancelled by the DC offset minimization by the parameter setting, of the transmitting part to an input terminal of the digital-to-analog converting circuit.

19. The wireless transceiver according to claim 4, wherein the wireless transceiver has a digital-to-analog converting circuit that converts transmission data from the controlling circuit from digital to analog as one of the plurality of circuit blocks forming the transmitting part, and the controlling circuit supplies a compensation value for canceling a residual DC offset, that is not cancelled by the DC offset minimization by the parameter setting, of the transmitting part to an input terminal of the digital-to-analog converting circuit.

20. The wireless transceiver according to claim 5, wherein the compensating part compensates for a mismatch in amplitude or phase between two signals in an orthogonal phase relationship in the transmitting part.

9. A wireless transmission method, comprising:

measuring a DC offset occurring in an amplifying circuit forming a receiving part that receives a signal transmitted by wireless;

selectively inputting an output signal of each of a plurality of circuit blocks having different functions forming a transmitting part that transmits a signal by wireless to the amplifying circuit and inputting the signal amplified by the amplifying circuit to an analog-to-digital converting circuit;

calculating a DC offset occurring in each of the plurality of circuit blocks by subtracting the DC offset occurring in the amplifying circuit from the output value of the analog-to-digital converting circuit; and

performing offset compensation to cancel or reduce the DC offset occurring in each of the plurality of circuit blocks based on the result of the calculation.