MEMORY SYSTEM

• US 20090089490A1
• Filed: 09/26/2008
• Published: 04/02/2009
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: OZAWA, Isao, OSHIMA, Takashi
• Granted Patent: US 8,131,912 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

A memory system including a nonvolatile memory, a first controller connected to a host equipment, the first controller controlling the entire memory system, a second controller connected to the first controller and also connected to the nonvolatile memory, the second controller controlling an access process to said nonvolatile memory, the second controller receives a command via the first controller and carries out the access process to the nonvolatile memory according to the command, the command being input from the host equipment.

Claims

1. A memory system comprising:

a nonvolatile memory;

a first controller connected to a host equipment, said first controller controlling the entire memory system; and

a second controller connected to said first controller and also connected to said nonvolatile memory, said second controller controlling an access process to said nonvolatile memory, said second controller receives a command via said first controller and carries out said access process to said nonvolatile memory according to said command, said command being input from said host equipment.

2. The memory system according to claim 1, wherein said second controller includes a first memory interface connected to said first controller, and a second memory interface connected to said nonvolatile memory, and said first memory interface and said second memory interface send and receive the same said command between said first controller and said nonvolatile memory.

3. The memory system according to claim 1, wherein said first controller and said second controller are constructed from separate semiconductor elements.

4. The memory system according to claim 1, wherein said memory system is constructed of a memory chip which includes said second controller and said nonvolatile memory.

5. The memory system according to claim 2, wherein said second controller includes an access path setting section which sets an access path which directly connects said first memory interface with said second memory interface, and said second controller and said nonvolatile memory are sealed within the same semiconductor package.

6. The memory system according to claim 5, wherein said access path setting section includes a first switch which switches between a first mode which connects said first memory interface with said second controller, and a second mode which connects said first memory interface with said access path, and also includes a second switch which switches between said first mode which connects said second memory interface and said second controller, and said second mode which connects said second memory interface and said access path.

7. The memory system according to claim 6, wherein said second controller includes a control section which outputs a control signal to said first switch and said second switch, said control signal controlling a switch between said first mode and said second mode according to a command sequence which instructs a shift operation to said second mode from said first mode which is received from said host equipment or instructs a return operation from said second mode to said first mode which is received from said host equipment.

8. The memory system according to claim 6, wherein said access path setting section detects a power supply input from said host equipment and sets said first switch and said second switch to said second mode.

9. The memory system according to claim 4, wherein said memory system includes a circuit substrate which forms a USB terminal which becomes a USB connector input/output terminal on one end of said circuit substrate, and said memory system is mounted with a semiconductor package which seals said second controller and said nonvolatile memory on said circuit substrate.

10. The memory system according to claim 1, wherein said nonvolatile memory is a NAND type flash memory.

11. A memory system comprising:

a plurality of nonvolatile memory;

a first controller connected to a host equipment, said first controller controlling the entire memory system; and

a second controller connected to said first controller and also connected to said plurality of nonvolatile memories, said second controller controlling an access process to said plurality of nonvolatile memories, said second controller receives a command via said first controller and carries out said access process to said plurality of nonvolatile memories according to said command, said command being input from said host equipment.

12. The memory system according to claim 11, wherein said second controller includes a counter which counts the number of times programming data which is input from said host equipment is reprogrammed, and changes the storage destination of said programming data among said plurality of nonvolatile memories based on the number of times said programming data is reprogrammed which is counted by said counter.

13. The memory system according to claim 12, wherein said plurality of nonvolatile memories includes a first nonvolatile memory and a second nonvolatile memory, each of which having a different storage capacity, and said counter counts the number of times said programming data is reprogrammed for each address within said first nonvolatile memory and each address within said second nonvolatile memory, and said second controller includes a storage section which stores the number of times said programming data is reprogrammed for each address within said first nonvolatile memory and each address within said second nonvolatile memory, and said second controller also includes a control section which changes a storage destination of said programming data to said second nonvolatile memory from said first nonvolatile memory or changes a storage destination of said programming data to said first nonvolatile memory from said second nonvolatile memory based on the number of times said programming data is reprogrammed for each address within said first nonvolatile memory stored in said storage section and based on the number of times said programming data is reprogrammed for each address within said second nonvolatile memory stored in said storage section.

14. The memory system according to claim 13, wherein said first nonvolatile memory has a storage capacity greater than said second nonvolatile memory and said second nonvolatile memory has a storage capacity smaller than said first nonvolatile memory, and said second controller includes a data distribution section which separates main data and additional data which are included in said programming data input from said host equipment, and distributes said main data to said first nonvolatile memory and stores said main data and distributes said additional data to said second nonvolatile memory and stores said additional data.

15. The memory system according to claim 11, wherein said second controller includes a first memory interface connected to said first controller, a second memory interface connected to said first nonvolatile memory, and a third interface memory connected to said second nonvolatile memory, and said first memory interface and said second memory interface send and receive the same said command between said first controller and said first nonvolatile memory, and said first memory interface and said third memory interface send and receive the same said command between said first controller and said second nonvolatile memory.

16. The memory system according to claim 15, wherein said second controller includes an access path setting section which sets an access path which directly connects said first memory interface, said second memory interface and said third memory interface.

17. The memory system according to claim 16, wherein said access path setting section includes a first switch which switches between a first mode which connects said first memory interface with said second controller, and a second mode which connects said first memory interface with said access path, and also includes a second switch which switches between said first mode which connects said second memory interface and said second controller, and said second mode which connects said second memory interface and said access path, and also includes a third switch which switches between said first mode which connects said third memory interface and said second controller and said second mode which connects said third memory interface with said access path.

18. The memory system according to claim 17, wherein said second controller includes a control section which outputs a control signal to said first switch, said second switch and said third switch, said control signal controlling a switch between said first mode and said second mode according to a command sequence which instructs a shift operation to said second mode from said first mode which is received from said host equipment or instructs a return operation from said second mode to said first mode which is received from said host equipment.

19. The memory system according to claim 11, wherein said memory system includes a circuit substrate which forms a USB terminal which becomes a USB connector input/output terminal on one end of said circuit substrate, and said memory system is mounted with a semiconductor package which seals said second controller and said plurality of nonvolatile memories on said circuit substrate.

20. The memory system according to claim 11, wherein said plurality of nonvolatile memories are NAND type flash memories.