Memory control apparatus, memory control method, and computer program

• US 20090089494A1
• Filed: 09/10/2008
• Published: 04/02/2009
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Koganezawa, Tomohiro
• Granted Patent: US 8,543,777 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed herein is a memory control apparatus including a plurality of memory control sections, each of which has connected thereto one or more memories that require periodic refresh and is configured to perform data write, data read, and refresh operations on the one or more memories. The memory control sections issue, to each of the one or more memories, refresh commands at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other.

Claims

1. A memory control apparatus, comprising

a plurality of memory control sections, each of which has connected to one or more memories that require periodic refresh and is configured to perform data write, data read, and refresh operations on the one or more memories,

wherein said memory control sections issue, to each of the one or more memories, refresh commands at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other.

2. The memory control apparatus according to claim 1,

wherein each of said memory control sections includes a memory control setting section configured to set a threshold number of conflicts of write/read commands and the refresh commands.

3. The memory control apparatus according to claim 2,

wherein the memory control setting section is capable of setting a maximum wait time for which issuance of a refresh request is suspended when the number of occurring conflicts exceeds the threshold number.

4. The memory control apparatus according to claim 3,

wherein, if the number of occurring conflicts continues to exceed the threshold number even after the maximum wait time has elapsed, one of said memory control sections causes one of said memory control sections that is continually performing a write/read operation on the memory to suspend issuance of the write/read commands upon completion of a current burst transfer.

5. A memory control apparatus, comprising

a memory control section that has connected to a plurality of memories that require periodic refresh and is configured to perform data write, data read, and refresh operations on the memories,

wherein said memory control section issues, to each of the memories, refresh commands at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other.

6. The memory control apparatus according to claim 5,

wherein said memory control section includes a memory control setting section configured to set a threshold number of conflicts of write/read commands and the refresh commands.

7. The memory control apparatus according to claim 6,

wherein the memory control setting section is capable of setting a maximum wait time for which issuance of a refresh request is suspended when the number of occurring conflicts exceeds the threshold number.

8. The memory control apparatus according to claim 7,

wherein, if the number of occurring conflicts continues to exceed the threshold number even after the maximum wait time has elapsed, said memory control section suspends issuance of the write/read commands upon completion of a current burst transfer.

9. A memory control method employed in a memory control apparatus including a plurality of memory control sections, each of which has connected to one or more memories that require periodic refresh and is configured to perform data write, data read, and refresh operations on the one or more memories, the method comprising the step of

issuing, to each of the one or more memories, refresh commands at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other.

10. A memory control method employed in a memory control apparatus including a memory control section that has connected to a plurality of memories that require periodic refresh and is configured to perform data write, data read, and refresh operations on the memories, the method comprising the step of

issuing, to each of the memories, refresh commands at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other.

11. A computer program for causing a computer to perform data write, data read, and refresh operations on one or more connected memories that require periodic refresh, the program causing the computer to perform the step of

issuing, to each of the one or more memories, refresh commands at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other.

12. A computer program for causing a computer to perform data write, data read, and refresh operations on a plurality of connected memories that require periodic refresh, the program causing the computer to perform the step of

issuing, to each of the memories, refresh commands at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other.