APPARATUS AND METHOD FOR ACCESSING A SYNCHRONOUS SERIAL MEMORY HAVING UNKNOWN ADDRESS BIT FIELD SIZE

• US 20090089530A1
• Filed: 09/27/2007
• Published: 04/02/2009
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Bodnar, John W.
• Granted Patent: US 7,542,365 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers

Abstract

An apparatus and method are provided for accessing a serial memory without knowing the required number of address bits. The apparatus comprises a pull circuit, a data out control circuit and a transition detector. The pull circuit causes the input terminal to be set to a first predetermined logic state in response to a read command being provided to the serial memory. The data out control circuit has an output terminal for providing the read command and a first predetermined number of address bits to the output terminal. The transition detector is coupled to an input terminal for detecting if the input terminal transitions from the first predetermined logic state to a second predetermined logic state in response to the first predetermined number of address bits. The transition detector will detect a transition of the input terminal when a correct number of address bits have been provided.

Claims

1. An apparatus comprising:

an input terminal for receiving data bits from a serial memory;

an output terminal for providing command and address bits to the serial memory;

a pull circuit for causing the input terminal to be set to a first predetermined logic state in response to a read command being provided to the serial memory;

a data out control circuit coupled to the output terminal, for causing the read command to be provided and for causing a first predetermined number of address bits to be provided to the output terminal; and

a transition detector, coupled to the input terminal, for detecting if the input terminal transitions from the first predetermined logic state to a second predetermined logic state in response to the first predetermined number of address bits;

wherein if the transition detector detects a transition of the input terminal, indicating that the first predetermined number of address bits is a correct number of address bits to access the memory, then receiving the data bits at the input terminal; and

wherein if the transition detector does not detect a transition of the input terminal, indicating that the first predetermined number of address bits is insufficient for accessing the memory, then providing a second predetermined number of address bits to the output terminal.

2. The apparatus of claim 1, wherein the pull circuit comprises a pull-up circuit having a first terminal coupled to a power supply voltage terminal, a second terminal for receiving an enable signal, and a third terminal coupled to the input terminal.

3. The apparatus of claim 1, wherein the serial memory is implemented as a standalone monolithic integrated circuit.

4. The apparatus of claim 1, further comprising:

a clock generator for providing a clock signal to the serial memory in response to receiving a system clock signal; and

a divider table, coupled to the clock generator, the divider table comprising a plurality of dividers for reducing a clock rate of the clock signal to substantially match a data rate at which the serial memory can transmit data bits.

5. The apparatus of claim 1, further comprising a processor coupled to the apparatus, wherein the serial memory is for storing boot data for the processor.

6. The apparatus of claim 1, wherein the serial memory comprises memory cells selected from a group consisting of flash, electrically erasable programmable read only memory (EEPROM), ferroelectric random access memory (FRAM), or magnetoresistive random access memory (MRAM) cells.

7. An apparatus comprising:

an input terminal for receiving data bits from a serial memory;

an output terminal for providing address bits to the serial memory;

a processor;

a serial boot facility, coupled to the processor, the serial boot facility for reading boot code and data from the serial memory in response to a reset of the processor, the serial boot facility comprising;

a pull circuit for causing the input terminal to be set to a first predetermined logic state in response to a read command being provided to the serial memory;

a data out control circuit, coupled to the output terminal, for causing the read command to be provided and for causing a first predetermined number of address bits to be provided to the output terminal; and

a transition detector, coupled to the input terminal, for detecting if the input terminal transitions from the first predetermined logic state to a second predetermined logic state in response to the first predetermined number of address bits;

wherein if the transition detector detects a transition of the input terminal, indicating that the first predetermined number of address bits is a correct number of address bits to access the memory, then receiving the data bits at the input terminal; and

wherein if the transition detector does not detect a transition of the input terminal, indicating that the first predetermined number of address bits is insufficient for accessing the memory, then providing a second predetermined number of address bits to the output terminal.

8. The apparatus of claim 7, wherein the pull circuit comprises a pull-up circuit having a first terminal coupled to a power supply voltage terminal, a second terminal for receiving a control signal, and a third terminal coupled to the input terminal.

9. The apparatus of claim 7, wherein the serial memory is implemented as a standalone monolithic integrated circuit.

10. The apparatus of claim 7, further comprising:

a clock generator for providing a clock signal to the serial memory in response to receiving a system clock signal; and

a divider table, coupled to the clock generator, the divider table comprising a plurality of dividers for reducing a clock rate of the clock signal to substantially match a data rate at which the serial memory can transmit data bits.

11. The apparatus of claim 7, wherein the serial memory comprises memory cells selected from a group consisting of flash, electrically erasable programmable read only memory (EEPROM), ferroelectric random access memory (FRAM), or magnetoresistive random access memory (MRAM) cells.

12. The apparatus of claim 7, further comprising a random access memory coupled to the processor, the random access memory for receiving the boot code and data read from the serial memory.

13. The apparatus of claim 7, wherein the first and second predetermined number of address bits are part of a continuous stream of address bits provided to the output terminal until the transition detector detects a transition on the input terminal.

14. A method for accessing a serial memory comprising:

providing a read command to access the serial memory;

setting an output terminal of the serial memory to a first predetermined logic state using a pull circuit;

providing a first predetermined number of address bits to the serial memory;

monitoring the output terminal to detect when the output terminal transitions from the first predetermined logic state to a second predetermined logic state, and if a transition is detected, indicating that the first predetermined number of address bits is a correct number of address bits for accessing the serial memory, receiving a predetermined number of data bits from the serial memory, and if a transition is not detected, indicating that the serial memory has not received a correct number of address bits, iteratively providing address bits until a transition is detected.

15. The method of claim 14, wherein providing a first predetermined number of address bits further comprises providing a one byte address to the serial memory.

16. The method of claim 14, wherein setting an output of the serial memory to a first predetermined logic state further comprises pulling the output terminal to a logic high state using a pull-up circuit.

17. The method of claim 14, further comprising:

disabling the pull circuit;

providing a predetermined number of clock edges to the serial memory;

receiving a predetermined number of data bits from the serial memory;

determining that all of the predetermined number of data bits have a same logic state; and

reading data from the serial memory.

18. The method of claim 17, further comprising:

determining an output data rate of the serial memory; and

setting a clock rate of an input clock signal provided to the serial memory to substantially match a data rate at which the serial memory can transmit data bits.

19. The method of claim 18, wherein setting a clock rate further comprises setting the clock rate by dividing a system clock rate by a divider selected from a plurality of dividers.

20. The method of claim 14, wherein the serial memory is accessed to provide boot code and data to a processor.