DIGEST GENERATION FROM INSTRUCTION OP-CODES

• US 20090089578A1
• Filed: 09/27/2007
• Published: 04/02/2009
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Johnson, Erik J., King, Steven R.
• Granted Patent: US 8,458,460 B2
• Time in Patent Office: Days
• US Class Current: 713/161
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC

Abstract

In general, in one aspect, a computer-implemented method includes determining a digest value based on hash operations on values of, at least, a set op-codes of multiple instructions of a program during execution of the program by a processor.

Claims

1. A computer-implemented method, comprising:

determining a digest value based on hash operations on values of, at least, a set op-codes of multiple instructions of a program during execution of the program by a processor.

2. The computer-implemented method of claim 1, wherein the hash operations do not operate on values stored in any operands of the instructions.

3. The computer-implemented method of claim 1, comprising performing at least one comparison based on the digest value and at least one expected value.

4. The computer-implemented method of claim 1, further comprising including data that is based on the determined digest value in a network packet.

5. The computer-implemented method of claim 1, further comprising:

receiving an instruction indicating that subsequently executed instructions should be included in the multiple instructions; and

receiving an instruction indicating that subsequently executed instructions should not included in the multiple instructions.

6. The computer-implemented method of claim 1, further comprising:

performing a transformation of a digest value in accordance with a processor key.

7. The computer-implemented method of claim 1, further comprising:

receiving an instruction that initializes the digest value.

8. A processor to execute program instructions, comprising:

logic to access instructions of a program; and

a data storage element to store a digest value based hash operations on values of, at least, a set op-codes of multiple instructions of the program during execution of the program by the processor.

9. The processor of claim 8, wherein the hash operations do not operate on values stored in any operands of the instructions.

10. The processor of claim 8, wherein the processor provides:

an instruction indicating that subsequently executed instructions should be included in the multiple instructions; and

an instruction indicating that subsequently executed instructions should not included in the multiple instructions.

11. The processor of claim 8, further comprising logic to perform a transformation of an intermediate value of the determined digest value in accordance with a processor key.

12. The processor of claim 8, wherein the processor provides:

an instruction that initializes the digest value.

13. A computer-implemented method, comprising:

accessing a value based on hash operations on values of, at least, a set op-codes of multiple instructions of a program during execution of the program by a processor; and

performing an operation based on the value and an expected value.

14. The computer-implemented method of claim 13, wherein the hash operations do not operate on values stored in any operands of the instructions.

15. The computer-implemented method of claim 13, wherein the value based on hash operations comprises a value included in a received network packet.

16. The computer-implemented method of claim 13, wherein the value based on hash operations comprises a transformation of a value of the hash operations by a key.