SEMICONDUCTOR DEVICES

• US 20090090950A1
• Filed: 10/05/2007
• Published: 04/09/2009
• Est. Priority Date: 10/05/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hanafi, Hussein I., Farnworth, Warren M., Farrar, Paul A., Bhattacharyya, Arup, Forbes, Leonard
• Granted Patent: US 7,875,529 B2
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures

Abstract

Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer.

Claims

1. A stacked wafer system having CMOS device logic circuitry, the system comprising:

at least one CMOS device, comprising;

a first wafer having NMOS transistors in a CMOS architecture;

a second wafer having PMOS transistors in the CMOS architecture; and

wherein the first wafer is electrically coupled to the second wafer.

2. The system of claim 1, wherein the first wafer is bonded and electrically coupled to the second wafer with a number of micro joints.

3. The system of claim 2, wherein the number of micro joints are micro solder balls having a diameter of not more than 5 microns.

4. The system of claim 3, wherein at least one of the CMOS devices is a three input logic circuit, the at least one three input logic circuit formed using at least three of the number of micro solder balls.

5. A stacked wafer system, comprising:

a DRAM cell, comprising;

a DRAM capacitor on a first wafer;

support circuitry associated with the DRAM capacitor on a second wafer; and

wherein the first wafer is electrically coupled to the second wafer.

6. The system of claim 5, wherein the system includes:

a number of DRAM capacitors on the first wafer; and

wherein the support circuitry includes a number of DRAM transistors that form a number of DRAM cells when the first wafer is bonded and electrically coupled to the second wafer and forms a number of DRAM cells.

7. The system of claim 6, wherein the number of DRAM capacitors includes at least one trench capacitor.

8. A stacked wafer system, comprising:

a first wafer having a number of vertical transistors coupled to a bit line;

a second wafer having amplifier circuitry associated with the number of vertical transistors; and

wherein the first wafer is electrically coupled to the second wafer.

9. The system of claim 8, wherein:

the first wafer includes a first bond pad formed thereon and coupled to the bit line;

the first bond pad is positioned on the first wafer so as to align with a second bond pad formed on the second wafer, the second bond pad coupled to a planar transistor of the amplifier circuitry; and

wherein a flowable interconnect is formed on at least one of the first and the second bond pad.

10. The system of claim 8, wherein the flowable interconnect is a reflowable interconnect that forms a micro solder ball having a diameter not greater than about 5 microns, the micro solder ball bonding and electrically coupling the first wafer to the second wafer.

11. The system of claim 8, wherein a number of capacitors are formed on the first wafer and coupled to the number of vertical transistors prior to the electrically coupling of the first and second wafer.

12. The system of claim 11, wherein the number of capacitors are trench capacitors, the trench capacitors and the number of vertical transistors form a number of DRAM cells on the first wafer.

13. The system of claim 12, wherein the amplifier circuitry includes a sense amplifier including a number of planar transistors.

14. The system of claim 13, wherein the sense amplifier circuitry includes only planar transistors.

15. A method for forming a CMOS device, the method comprising:

forming a number of NMOS transistors on a first wafer using an NMOS process;

forming a number of PMOS transistors on a second wafer using a PMOS process; and

bonding the first wafer and the second wafer to form at least one CMOS device.

16. The method of claim 15, wherein bonding includes electrically coupling in a manner that enables signal processing CMOS logic between the first wafer and the second wafer.

17. The method of claim 15, wherein the at least one CMOS device includes at least one of the number of NMOS transistors and at least one of the number of PMOS transistors;

and

wherein the method includes forming a first reflowable interconnect on at least one of a first bond pad formed on the first wafer and a second bond pad formed on the second wafer, the first bond pad coupled to the at least one of the number of NMOS transistors and the second bond pad coupled to the at least one of the number of PMOS transistors.

18. The method of claim 17, wherein the method includes bonding a third wafer to the at least one of the first and the second wafer, wherein bonding the third wafer includes using a second reflowable interconnect, the second reflowable interconnect having different material properties from the first reflowable interconnect.

19. The method of claim 15, wherein the method includes bonding and electrically coupling the first wafer and the second wafer to form at least one static random access memory cell.

20. A method for forming a memory device, comprising:

forming a number of DRAM capacitors on a first wafer;

separately forming support circuitry associated with the DRAM capacitors on a second wafer, the support circuitry including;

a number of transistors to be coupled to the number of DRAM capacitors to form a number of DRAM cells; and

a bit line coupled to at least one of the number of transistors; and

electrically coupling the first wafer and the second wafer to form the number of DRAM cells.

21. The method of claim 20, wherein electrically coupling includes coupling the number of DRAM capacitors formed on the first wafer to the number of transistors formed on the second wafer via a number of micro solder balls.

22. The method of claim 21, wherein at least some of the number of DRAM capacitors are trench capacitors, and wherein the method includes forming the at least some trench capacitors using a high dielectric constant material.

23. The method of claim 20, wherein the method includes bonding and electrically coupling the first wafer and the second wafer via a number of micro solder balls having a diameter of not more than 2 microns.

24. The method of claim 20, wherein forming the support circuitry includes forming sense amplifier circuitry on the second wafer.

25. The method of claim 20, wherein forming the support circuitry includes forming a number of vertical transistors on the second wafer.