Nonvolatile semiconductor memory and method of manufacturing the same

• US 20090090962A1
• Filed: 09/30/2008
• Published: 04/09/2009
• Est. Priority Date: 10/04/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Kikuchi, Takeshi
• Granted Patent: US 7,973,356 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A nonvolatile semiconductor memory device includes: a semiconductor substrate; a first gate electrode formed on the semiconductor substrate through a gate insulating film; a second gate electrode formed in a side direction of the first gate electrode and electrically insulated from the first gate electrode; and an insulating film formed at least between the semiconductor substrate and the second gate electrode to trap electric charge, as an electric charge trapping film. The first gate electrode comprises a lower portion contacting the gate insulating film and an upper portion above the lower portion of the first gate electrode, and a distance between the upper portion of the first gate electrode and the second gate electrode is longer than a distance between the lower portion of the first gate electrode and the second gate electrode.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a first gate electrode formed on said semiconductor substrate through a gate insulating film;

a second gate electrode formed in a side direction of said first gate electrode and electrically insulated from said first gate electrode; and

an insulating film formed at least between said semiconductor substrate and said second gate electrode to trap electric charge, as an electric charge trapping film,

wherein said first gate electrode comprises a lower portion contacting said gate insulating film and an upper portion above said lower portion of said first gate electrode, and

a distance between said upper portion of said first gate electrode and said second gate electrode is longer than a distance between said lower portion of said first gate electrode and said second gate electrode.

2. The nonvolatile semiconductor memory device according to claim 1, wherein said electric charge trapping film exists between said first gate electrode and said second gate electrode, as well as between said semiconductor substrate and said second gate electrode.

3. The nonvolatile semiconductor memory device according to claim 2, wherein said electric charge trapping film is provided between said lower portion of said first gate electrode and said second gate electrode, and

said electric charge trapping film and a first insulating film are provided between said upper portion of said first gate electrode and said second gate electrode.

4. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a silicide layer formed on said first gate electrode.

5. The nonvolatile semiconductor memory device according to claim 4, wherein said silicide layer is provided on the surface of said first gate electrode.

6. The nonvolatile semiconductor memory device according to claim 1, wherein said second gate electrode is provided on each side of said first gate electrode.

7. The nonvolatile semiconductor memory device according to claim 1, wherein said electric charge trapping film is an ONO (Oxide Nitride Oxide) film.

8. The nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a first gate electrode formed through a gate insulating film on said semiconductor substrate;

a second gate electrode formed in a side direction of said first gate electrode and electrically insulated from said first gate electrode; and

an insulating film formed at least between said semiconductor substrate and said second gate electrode as an electric charge trapping film to trap electric charge,

wherein a section shape of said first gate electrode in a plane perpendicular to said semiconductor substrate and a direction in which said first gate electrode extends is perpendicular to the surface of is a convex shape.