HIGH DENSITY FET WITH INTEGRATED SCHOTTKY

• US 20090090966A1
• Filed: 09/30/2008
• Published: 04/09/2009
• Est. Priority Date: 10/04/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: THORUP, PAUL, Rexer, Christopher Lawrence
• Granted Patent: US 8,686,493 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode

Abstract

A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween.

Claims

1-12. -12. (canceled)

13. A semiconductor structure including a monolithically integrated trench FET and Schottky diode, the semiconductor structure comprising:

a plurality of trenches extending into a semiconductor region of a first conductivity type;

a gate electrode in each trench;

first and second body regions of a second conductivity type over the semiconductor region between first and second pair of adjacent trenches, respectively;

a source region of the first conductivity type over the first body region;

a recess extending between each of the first and second adjacent trenches and terminating in the semiconductor region at a depth below the first and second body regions; and

an interconnect layer extending into each recess to electrically contact the source region and the first and second body regions, the interconnect layer further contacting the semiconductor region along a bottom of each recess to form a Schottky contact therebetween, the interconnect layer forming an anode terminal of the Schottky diode and a source electrode of the FET.

14. The semiconductor structure of claim 13 the first body region has an upper surface below an upper surface of the gate electrode, and the second body region vertically extends above the upper surface the gate electrode.

15. The semiconductor structure of claim 13 wherein each recess has tapered edges and is self aligned with the trenches.

16. The semiconductor structure of claim 13 further comprising:

a shield electrode in a lower portion of each trench below the gate electrode, the shield electrode being insulated from the semiconductor region by a shield dielectric;

an inter-electrode dielectric extending between the shield electrode and gate electrode in each trench; and

a gate dielectric lining upper trench sidewalls of each trench.

17. The semiconductor structure of claim 13 wherein the gate electrode is recessed in each trench and is capped with a dielectric material.

18. The semiconductor structure of claim 13 wherein the interconnect layer further comprises a barrier metal layer which forms a Schottky contact with the semiconductor region along a bottom of each recess.

19. The semiconductor structure of claim 13 further comprising a thick bottom dielectric below the gate electrode in each trench.

20. The semiconductor structure of claim 13 further comprising a plurality of heavy body regions of the second conductivity type over and in contact with the first body region.

21. The semiconductor structure of claim 13 wherein during operation, a conduction channel is formed in the first body region but not in the second body region.

22. The semiconductor structure of claim 13 wherein when the FET is turned on, a current flows through the first body region but not through the second body region.

23. The semiconductor structure of claim 13 further comprising a doped region in the semiconductor region along the bottom of each recess where the Schottky contact is formed.

24. A method for forming a semiconductor structure comprising a monolithically integrated trench FET and Schottky diode, the method comprising:

forming a plurality of trenches extending into a semiconductor region of a first conductivity type;

forming a gate electrode in each trench;

forming first and second body regions in the semiconductor region between a first pair of adjacent trenches and a second pair of adjacent trenches, respectively;

forming a doped region of the first conductivity type in the first body region but not in the second body region;

forming a recess between each of the first and second adjacent trenches, each recess terminating in the semiconductor region below the first and second body regions, the recess between the first adjacent trenches dividing the doped region into two doped regions, each of the two doped regions forming a source region; and

forming an interconnect layer extending into each recess to electrically contact sidewalls of the source regions and the first and second body regions, the interconnect layer further contacting the semiconductor region along a bottom of each recess to form a Schottky contact therebetween, the interconnect layer forming an anode terminal of the Schottky diode and a source electrode of the FET.

25. The method of claim 24 wherein forming the recesses comprises using a silicon etch process without a mask such that the recesses are self aligned with the trenches.

26. The method of claim 24 wherein each recess has tapered edges and extends from upper corners of the two adjacent trenches through the doped region and the first and second body regions.

27. The method of claim 24 wherein the gate electrode is recessed in each trench, the method further comprising capping the gate electrode in each trench with a dielectric material so that a top surface of the dielectric material is coplanar with a top surface of the semiconductor region.

28. The method of claim 24 wherein forming the interconnect layer further comprises forming a barrier metal layer to thereby form a Schottky contact with the semiconductor substrate along the bottom of each recess.

29. The method of claim 24 further comprising:

prior to forming the interconnect layer, implanting dopants in each recess to form an implant region in the semiconductor region along the bottom of each recess where the Schottky contact is formed.

30. The method of claim 24 further comprising:

prior to forming the gate electrode;

forming a shield dielectric along lower sidewalls and bottom of each trench;

forming a shield electrode in a lower portion of each trench, the shield electrode being insulated from the semiconductor region by the shield dielectric;

forming an inter-electrode dielectric extending over the shield electrode in each trench.

31. The method of claim 24 further comprising:

prior to forming the gate electrode;

forming a thick bottom dielectric along a bottom of each trench; and

forming a gate dielectric along sidewalls of each trench, the gate dielectric being thinner than the thick bottom dielectric.

32. A semiconductor structure comprising a monolithically integrated trench FET and Schottky diode, the semiconductor structure further comprising:

a plurality of trenches extending into a semiconductor region of a first conductivity type;

a gate electrode in each trench;

first and second body regions of a second conductivity type over the semiconductor region between a first and second pair of adjacent trenches, respectively;

source regions of the first conductivity type over the first body region;

a first recess extending between the first pair of trenches and terminating in the first body region at a depth below the source regions;

a second recess extending between the second pair of trenches and terminating in the semiconductor region at a depth below the first, second and third body regions; and

an interconnect layer extending into the first and second recesses to electrically contact the source regions and the first and second body regions, the interconnect layer further contacting the semiconductor region along a bottom of the second recess to form a Schottky contact therebetween, the interconnect layer forming an anode terminal of the Schottky diode and a source electrode of the FET.

33. The semiconductor structure of claim 32 further comprising:

a shield electrode in a lower portion of each trench below the gate electrode, the shield electrode being insulated from the semiconductor region by a shield dielectric;

an inter-electrode dielectric extending between the shield electrode and gate electrode in each trench; and

a gate dielectric lining upper trench sidewalls of each trench.

34. The semiconductor structure of claim 32 further comprising a thick bottom dielectric below the gate electrode in each trench.

35-37. -37. (canceled)