SOI SUBSTRATE CONTACT WITH EXTENDED SILICIDE AREA

• US 20090090970A1
• Filed: 10/08/2007
• Published: 04/09/2009
• Est. Priority Date: 10/08/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dang, Dinh, Slinkman, James Albert, Doan, Thai, Levy, Max Gerald, Levy, Jessica Anne, Norris, Alan Frederick
• Granted Patent: US 7,675,121 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Claims

1. A structure, comprising:

dielectric isolation in an upper silicon layer of a substrate, said substrate comprising a buried oxide layer between said upper silicon layer and a lower silicon layer, said dielectric isolation extending from a top surface of said upper silicon layer to said buried oxide layer, said dielectric isolation surrounding a perimeter of contact region of said upper silicon layer;

a polysilicon region extending through said contact region and through said buried oxide layer to said lower silicon layer, portions of said contact region remaining between said polysilicon region and said dielectric isolation, said polysilicon region doped a same dopant type as said lower silicon layer; and

a contiguous metal silicide layer in remaining portions of said contact region and said polysilicon region, said metal silicide layer extending from a top surface of said polysilicon region into said polysilicon region and extending from a top surface of said remaining portions of said contact region into said remaining portions of said contact region.

2. The structure of claim 1, further including:

an enhanced contact region in said lower silicon layer, abutting a bottom of said polysilicon region, said enhanced contact region doped said same dopant type as said lower silicon layer.

3. The structure of claim 2, wherein a polysilicon region/lower silicon layer interface has a resistivity of about 0.05 or less.

4. The structure of claim 1, further including:

a top surface of said polysilicon region recessed below a top surface of said dielectric isolation.

5. The structure of claim 1, wherein said lower silicon layer and said upper silicon layer are doped P-type.

6. The structure of claim 1, wherein a width of said contact region measured in a direction parallel to a top surface of said upper silicon layer is less than a width of said contact region measured in said direction.

7. The structure of claim 1, wherein a ratio of a total thickness of said upper silicon layer and said buried oxide layer measured in a direction perpendicular to said top surface of said upper silicon layer to a width of said polysilicon region measured in a direction perpendicular to said top surface of said upper silicon layer is equal to or greater than about 3.

8. The structure of claim 1, wherein said polysilicon region does not physically contact said dielectric isolation.

9. The structure of claim 1, wherein at least a portion of said contact region intervenes between said dielectric isolation and said polysilicon region.

10. The structure of claim 1, wherein said contact region is in the form of a first ring surrounded by said dielectric isolation and said polysilicon region is in the form of a second ring within said first ring.

11. A structure, comprising:

a dielectric isolation in an upper silicon layer of a substrate, said substrate comprising a buried oxide layer between said upper silicon layer and a lower silicon layer, said dielectric isolation extending from a top surface of said upper silicon layer to said buried oxide layer, said dielectric isolation surrounding a perimeter of a contact region of said upper silicon layer and surrounding a perimeter of a device region of said upper silicon layer;

a polysilicon region extending through said contact region and through said buried oxide layer to said lower silicon layer, portions of said contact region remaining between said polysilicon region and said dielectric isolation;

a gate dielectric layer between a gate electrode and a portion of said device region;

source/drain regions of a same dopant type as said lower silicon layer in said device region on opposite sides of said gate electrode; and

metal silicide layers in remaining portions of said contact region, said polysilicon region and said source/drain regions;

said metal silicide layers extending from respective top surfaces of said polysilicon region into said polysilicon region, of said remaining portions of said contact region into said remaining portions of said contact region and of said source/drain regions into said source/drain regions, said metal silicide layers in said remaining portions of said contact region and said polysilicon region being contiguous.

12. The structure of claim 11, further including:

an enhanced contact region in said lower silicon layer, said enhanced contact region abutting a bottom of said polysilicon region, said enhanced contact region doped said same dopant type as said lower silicon layer.

13. The structure of claim 12, wherein a polysilicon region/lower silicon layer interface has a resistivity of about 0.05 or less.

14. The structure of claim 11, further including:

a top surface of said polysilicon region recessed below a top surface of said dielectric isolation.

15. The structure of claim 11, wherein said lower silicon layer, said upper silicon layer are doped P-type.

16. The structure of claim 11, wherein a width of said contact region measured in a direction parallel to a top surface of said upper silicon layer is less than a width of said contact region measured in said direction.

17. The structure of claim 11, wherein a ratio of a total thickness of said upper silicon layer and said buried oxide layer measured in a direction perpendicular to said top surface of said upper silicon layer to a width of said polysilicon region measured in a direction perpendicular to said top surface of said upper silicon layer is equal to or greater than about 3.

18. The structure of claim 11, wherein said polysilicon region does not physically contact said dielectric isolation.

19. The structure of claim 11, wherein at least a portion of said contact region intervenes between said dielectric isolation and said polysilicon region.

20. The structure of claim 12, wherein said contact region is in the form of a first ring surrounded by said dielectric isolation and said polysilicon region is in the form of a second ring within said first ring.