PROCESS FOR INTEGRATING PLANAR AND NON-PLANAR CMOS TRANSISTORS ON A BULK SUBSTRATE AND ARTICLE MADE THEREBY

• US 20090090976A1
• Filed: 12/11/2008
• Published: 04/09/2009
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Kavalieros, Jack T., Doczy, Mark L., Doyle, Brian S., Brask, Justin K., Metz, Matthew V., Datta, Suman
• Granted Patent: US 8,193,567 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.

Claims

1. A microprocessor comprising:

a cache region on a bulk semiconductor substrate including a first and a second non-planar SRAM transistor, wherein the first non-planar SRAM transistor includes a single non-planar semiconductor body having a first gate-coupled sidewall height; and

a second region on the bulk semiconductor substrate, the second region including a second multi-gate transistor having a single non-planar semiconductor body with a second gate-coupled sidewall height, different than the first gate coupled sidewall height, to form two multi-gate transistors of differing performance within the microprocessor.

2. The microprocessor of claim 1, wherein the second region is a second cache memory region and wherein the second multi-gate transistor is a second multi-gate SRAM transistor to form first and second SRAM transistors of differing performance within the microprocessor cache.

3. The microprocessor of claim 2, wherein the first and second non-planar SRAM transistors occupy a substantially equal-sized layout area within the cache region of the microprocessor.

4. The microprocessor of claim 1, wherein the single non-planar semiconductor body of the first multi-gate SRAM transistor further comprises a first active region having a first top surface and wherein the single non-planar semiconductor body of the second multi-gate transistor further comprises a second active area having a second top surface substantially coplanar with the first top surface.

5. The microprocessor as in claim 4,

wherein the first active region has sidewalls extending a first height above a top surface of an adjacent first isolation region on the bulk semiconductor substrate;

and

wherein the second active region has sidewalls extending a second height, different than the first, above a top surface of an adjacent second isolation region on the bulk semiconductor substrate;

wherein the gate-coupled sidewall height of each multi-gate device is greater than a width of a top surface of each of the first and second active regions; and

wherein an interface between the first and second isolation regions and the bulk semiconductor is coplanar.

6. The microprocessor of claim 5, wherein the first isolation region is contiguous with the second isolation region, a transition between the first and second isolation regions having a step of a height approximately equal to the difference in the gate coupled sidewall heights.

7. The microprocessor of claim 1, wherein the first non-planar SRAM transistor further comprises:

a first gate insulator adjacent to at least a portion of the first active region sidewalls;

a first gate electrode on the first gate insulator; and

a first pair of source/drain regions on opposite sides of the first gate electrode;

a first pair of source/drain regions on opposite sides of the first gate electrode; and

wherein the second non-planar SRAM transistor further comprises;

a second gate insulator adjacent to at least a portion of the second active region sidewalls;

a second gate electrode on the second gate insulator; and

a second pair of source/drain regions on opposite sides of the second gate electrode; and

a second pair of source/drain regions on opposite sides of the second gate electrode.

8. The microprocessor of claim 7, wherein the first gate insulator is on a top surface of the first active region and the first gate electrode is on the first gate insulator to form a tri-gate SRAM transistor.

9. The microprocessor of claim 7, wherein the first gate electrode and the second gate electrode are physically connected.

10. The microprocessor of claim 7, wherein the first and second gate electrodes comprise a metal and wherein the first and second gate insulators comprise a metal oxide.

11. The microprocessor of claim 2, further comprising a core logic region including a planar transistor.

12. The microprocessor of claim 11, wherein the planar transistor further comprises:

a third active region having sidewalls substantially covered by an adjacent third isolation region on the bulk semiconductor substrate;

a third gate insulator on a top surface of the third active region;

a third gate electrode on the third gate insulator; and

a third pair of source/drain regions on opposite sides of the third gate electrode.

13. The microprocessor of claim 12, wherein a top surface of the third active region is coplanar with both the first second active regions.

14. The microprocessor of claim 11, wherein the planar transistor has a larger current carrying channel width than at least one of the first and second non-planar SRAM transistors.

15. The microprocessor of claim 11, wherein the channel regions of the first and second non-planar SRAM transistors are undoped and wherein the channel region of the planar transistor is doped.