LOW VOLTAGE DIFFERENTIAL SIGNALLING DRIVER

• US 20090091357A1
• Filed: 10/04/2007
• Published: 04/09/2009
• Est. Priority Date: 10/04/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kommareddi, Sankarareddy S., Muniyappa, Vishwanath
• Granted Patent: US 7,551,006 B2
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission

Abstract

A low voltage differential signal (LVDS) driver comprising a cascade current source circuit coupled to a positive voltage supply configured to supply a current, a cascade current sink circuit maintained at a ground voltage configured to receive the current; the cascade current source circuit being coupled to the cascade current sink circuit by a current switching circuit being provided by a positive voltage supply from the cascade current source circuit and with complementary logic signals, the current switching circuit configured to provide a constant differential output voltage while in operation. Other embodiments are also disclosed.

Claims

1. A low voltage differential signal (LVDS) driver comprising:

a cascade current source circuit coupled to a positive voltage supply configured to supply a current;

wherein the cascade current source circuit configured to provide a positive voltage supply comprises a first PMOS and a second PMOS configured to receive a high bias voltage and a third PMOS and a fourth PMOS configured to receive a low bias voltage;

a cascade current sink circuit maintained at a ground voltage configured to receive the current;

the cascade current source circuit being coupled to the cascade current sink circuit by a current switching circuit being provided by a positive voltage supply from the cascade current source circuit and with complementary logic signals, the current switching circuit configured to provide a constant differential output voltage while in operation.

3. The LVDS driver of claim 1, wherein the cascade current sink circuit configured to receive a current and maintained at the ground voltage comprises a first NMOS and a second NMOS configured to receive a high bias voltage and a third NMOS and a fourth NMOS configured to receive a low bias voltage.

4. The LVDS driver of claim 1, wherein the current switching circuit comprises a plurality of PMOSs and NMOSs coupled in pairs to form a plurality of transmission gates.

5. The LVDS driver of claims 4, wherein each transmission gate comprises a PMOS and an NMOS in combination.

6. The LVDS driver of claim 5, wherein in a first and a second transmission gates the NMOS receive a logic signal 1 and the PMOS receives a logic signal 0.

7. The LVDS driver of claim 5, wherein in the third and fourth transmission gates the PMOS receives a logic signal 1 and the NMOS receives a logic signal 0.

8. The LVDS driver of claim 1, wherein the differential output from the current switching circuit is provided to a terminator unit.

9. The LDVS circuit of claim 8, wherein the differential output from the terminator unit is provided to a receiver over a communication medium.

10. The LVDS of claim 9, wherein the communication medium is a cable.

2. (canceled)

11. A circuit comprising a low voltage differential signal (LVDS) driver comprising:

a cascade current source circuit coupled to a positive voltage supply configured to supply a current;

wherein the cascade current source circuit configured to provide a positive voltage supply comprises a first PMOS and a second PMOS configured to receive a high bias voltage and a third PMOS and a fourth PMOS configured to receive a low bias voltage;

a cascade current sink circuit maintained at a ground voltage configured to receive the current;

the cascade current source circuit being coupled to the cascade current sink circuit by a current switching circuit being provided by a positive voltage supply from the cascade current source circuit and with complementary logic signals, wherein the current switching circuit configured to provide a constant differential output voltage;

the cascade current source circuit, the cascade current sink circuit and the current switching circuit along with a termination unit forming a transmission block and coupled to a receiver block by means of a cable.

12. The circuit of claim 11, wherein the cable comprises conducting metallic materials.

14. The circuit of claims 11, wherein the cascade current sink circuit configured to receive a current and maintained at the ground voltage comprises a first NMOS and a second NMOS configured to receive a high bias voltage and a third NMOS and a fourth NMOS configured to receive a low bias voltage.

15. The circuit of claims 11, wherein the current switching circuit comprises a plurality of PMOSs and NMOSs coupled in pairs to form a plurality of transmission gates, and each transmission gate comprising a combination of a PMOS and an NMOS.

16. The circuit of claims 15, wherein the current switching circuit comprises four transmission gates the first transmission gate a NMOS receive a logic signal 1, the second transmission gate a PMOS receives a logic signal 0, the third transmission gate a PMOS receives a logic signal 1 and the fourth transmission gate a NMOS receives a logic signal 0.

17. The circuit of claims 11, wherein the differential output from the current switching circuit is provided to a terminator unit, and the differential output from the terminator unit is provided to a receiver over a communication medium.

13. (canceled)

18. A circuit comprising:

means for generating a current supply, wherein the means for generating the current supply comprises a cascade current source circuit coupled to a positive voltage supply;

wherein the cascade current source circuit configured to provide a positive voltage supply comprises a first PMOS and a second PMOS configured to receive a high bias voltage and a third PMOS and a fourth PMOS configured to receive a low bias voltage and the cascade current sink circuit configured to receive a current and maintained at the ground voltage comprises a first NMOS and a second NMOS configured to receive a high bias voltage and a third NMOS and a fourth NMOS configured to receive a low bias voltage;

means for receiving a current, wherein the means for receiving the current comprises a cascade current sink circuit maintained at a ground voltage;

means for providing a constant differential output voltage, wherein the means comprises a current switching circuit coupled to the cascade current source circuit and to the cascade current sink circuit by a current switching circuit being provided by a positive voltage supply from the cascade current source circuit and with complementary logic signals.

20. The circuit of claims 18, wherein the current switching circuit comprises a plurality of PMOSs and NMOSs coupled in pairs to form a plurality of transmission gates, and each transmission gate comprising a combination of a PMOS and an NMOS;

and the current switching circuit comprising four transmission gates the first transmission gate a NMOS receive a logic signal 1, the second transmission gate a PMOS receives a logic signal 0, the third transmission gate a PMOS receives a logic signal 1 and the fourth transmission gate a NMOS receives a logic signal 0.

21. The circuit of claims 18, further comprising:

means for transmitting the constant differential output voltage;

means for communicating the differential output voltage;

means for receiving the differential output voltage.

19. (canceled)

22. A low voltage differential signal (LVDS) driver comprising:

a cascade current source circuit coupled to a positive voltage supply configured to supply a current;

wherein the cascade current sink circuit configured to receive a current and maintained at the ground voltage comprises a first NMOS and a second NMOS configured to receive a high bias voltage and a third NMOS and a fourth NMOS configured to receive a low bias voltage;

a cascade current sink circuit maintained at a ground voltage configured to receive the current;

the cascade current source circuit being coupled to the cascade current sink circuit by a current switching circuit being provided by a positive voltage supply from the cascade current source circuit and with complementary logic signals, the current switching circuit configured to provide a constant differential output voltage while in operation.