Statistical Switched Capacitor Droop Sensor for Application in Power Distribution Noise Mitigation

• US 20090091378A1
• Filed: 10/09/2007
• Published: 04/09/2009
• Est. Priority Date: 10/09/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Haridass, Anand, Weekly, Roger D., O'Reilly, Colm B.
• Granted Patent: US 7,818,599 B2
• Time in Patent Office: Days
• US Class Current: 327/554
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision

Abstract

A circuit and a method for detecting noise events in a system with time variable operating points is provided. A switched capacitor filter comprising a plurality of capacitor units, samples a first voltage to determine an average of a set of voltage measurements, forming an average voltage. A filter control unit controls the plurality of capacitor units in the switched capacitor filter. A comparing unit compares the average voltage to the first voltage to form a comparison. A signaling unit generates a signal to instruct circuits in a processor to initiate actions to keep the first voltage from drooping below a threshold level in response to the comparison.

Claims

1. A circuit for detecting noise events in a system with time variable operating points, said circuit comprising:

a switched capacitor filter comprising a plurality of capacitor units for sampling a first voltage to determine an average of a set of voltage measurements, forming an average voltage;

a filter control unit for controlling the plurality of capacitor units in the switched capacitor filter;

a comparing unit for comparing the average voltage to the first voltage to form a comparison; and

a signaling unit for generating a signal to instruct circuits in a processor to initiate actions to keep the first voltage from drooping below a threshold level in response to the comparison.

2. The circuit of claim 1, wherein the comparing unit comprises a plurality of comparators and a voting block.

3. The circuit of claim 1, wherein the filter control unit comprises:

a master filter control state machine;

a phase select state machine;

a cycle discharging control signal state machine;

a plurality of AND gates; and

a plurality of NOT gates.

4. The circuit of claim 3, wherein the cycle discharging control signal state machine determines that a discharging control signal rather than a charging control signal should be activated when a master filter control state machine activates a global charging control signal.

5. The circuit of claim 4, wherein the cycle discharging control signal state machine is cycled between a first state and a second state by the master filter control state machine.

6. The circuit of claim 5, wherein the first state indicates that a discharging control signal should be activated when the master filter control state machine activates the global charging control signal.

7. The circuit of claim 5, wherein the second state indicates that a charging control signal should be activated when the master filter control state machine activates the global charging control signal.

8. The circuit of claim 3, wherein the phase select state machine determines which capacitor unit of the plurality of capacitor units samples the first voltage during a sampling period.

9. The circuit of claim 8, wherein a capacitor unit of the plurality of capacitor units samples the first voltage during a sampling period when a charging control signal input of the capacitor unit is in an on state and a strong switch charge averaging control signal input of the capacitor unit is in an off state.

10. The circuit of claim 8, wherein a default setting of a charging control signal input state and a strong switch charge averaging control signal input state for each capacitor unit of the plurality capacitor units is the charging control input state set to off and the strong switch charge averaging control signal input state set to on.

11. The circuit of claim 3, wherein the master filter control state machine determines the sample rate of the switched capacitor filter.

12. The circuit of claim 11, wherein the master filter control state machine is configured by a first parameter to control a time delay between activations of a charging control signal, a discharging control signal, a strong switch charge averaging control signal, a weak switch charge averaging control signal and wherein the master filter control state machine is configured by a second parameter to control a delay between activating the strong switch charge averaging control signal and the weak switch charge averaging control signal.

13. The circuit of claim 12, wherein the second parameter is set to assure that the weak switch charge averaging control signal is activated for a period of time that allows the plurality of capacitor units to be at about the same voltage before activating the strong switch charge averaging control signal.

14. The circuit of claim 11, wherein the master filter phase control machine determines when the phase select state machine and the cycle discharging control signal state machine change states.

15. The circuit of claim 1, wherein the signal is generated in response to the first voltage being lower than the average voltage by a specified criteria.

16. The circuit of claim 1, wherein the signal is generated in response to the first voltage being higher than the average voltage by a second specified criteria.

17. The circuit of claim 1, wherein each capacitor unit of the plurality of capacitor units comprises:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor; and

a capacitor.

18. The circuit of claim 17, wherein the first transistor is controlled by a charging control signal from the filter control unit;

wherein the second transistor is controlled by a strong switch charge averaging control signal from the filter control unit;

wherein the third transistor is controlled by a discharging control signal from the filter control unit; and

wherein the fourth transistor is controlled by a weak switch charge averaging control signal from the filter control unit.

19. The circuit of claim 1, wherein the plurality of capacitor units comprises thirty-two capacitor units.

20. A method for detecting circuit noise events in a system with time variable operating points, said method comprising:

sampling a first voltage by a plurality of capacitor units to determine an average of a set of voltage measurements, forming an average voltage;

comparing the average voltage to the first voltage to form a comparison; and

generating a signal to instruct circuits in a processor to initiate actions to keep the first voltage from drooping below a threshold level in response to the comparison.

21. The method of claim 20, wherein comparing the average voltage to the first voltage to form a comparison comprises:

comparing the average voltage to the first voltage by a plurality of comparators; and

summarizing results of the comparators by a voting block to form a comparison.

22. The method of claim 20, further comprises:

controlling a timing for sampling the first voltage for each capacitor unit in the plurality of capacitor units; and

controlling a duration for sampling the first voltage for each capacitor unit in the plurality of capacitor units.

23. The method of claim 22, further comprising:

configuring a first parameter to control a time delay between activations of a charging control signal, a discharging control signal, a strong switch charge averaging control signal, and a weak switch charge averaging control signal.

24. The method of claim 23, further comprising:

configuring a second parameter to control a delay between activating the strong switch charge averaging control signal and the weak switch charge averaging control signal.

25. The method of claim 23, further comprising:

determining whether a discharging control signal or a charging control signal should be activated when a signal to activate a global charging control signal is received.