MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACKING MEMORY CHIPS, AND METHOD OF CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY

• US 20090091962A1
• Filed: 09/26/2008
• Published: 04/09/2009
• Est. Priority Date: 10/04/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHUNG, Hoe-ju, LEE, Jung-bae, KANG, Uk-song
• Granted Patent: US 7,830,692 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips.

Claims

1. A multi-chip memory device comprising:

a transfer memory chip communicating input/output signals;

a stacked plurality of memory chips disposed on the transfer memory chip, wherein each one of the stacked plurality of memory chips comprises a memory array having a designated bank; and

a signal path extending upward from the transfer memory chip through the stacked plurality of memory chips to communicate at least one of the input/output signals to each bank of each memory chip in the stacked plurality of memory chips;

wherein respective banks of each memory chip in the stacked plurality of memory chips are commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips.

2. The multi-chip memory device of claim 1, wherein the signal path is implemented by at least one through silicon via (TSV) formed through a substrate of one of the stacked plurality of memory chips.

3. The multi-chip memory device of claim 1, wherein the at least one of the input/output signals comprises at least one of a read/write command, an address corresponding to the read/write command, a clock signal associated with the read/write command, and data associated with the read/write command.

4. The multi-chip memory device of claim 3, wherein the read/write command is associated with a burst length defining a number of data bits provided by the read operation or a number of data bits associated with write data associated with the write operation.

5. The multi-chip memory device of claim 4, wherein the stacked plurality of memory chips comprises N memory chips and the burst length defines B data bits, and in response to the read operation, each commonly addressed bank in the N memory chips provides a data block of B/N bits to the transfer memory chip via the signal path.

6. The multi-chip memory device of claim 4, wherein the stacked plurality of memory chips comprises N memory chips and the burst length defines B data bits, and in response to the write operation, each commonly addressed bank in the N memory chips receives a data block of B/N bits from the transfer memory chip via the signal path.

7. The multi-chip memory device of claim 1, wherein the stacked plurality of memory chips comprises first and second memory chips and the first memory chip comprises:

a command control unit delaying application of either a read command associated with the read operation or write command associated with the write operation to the second memory chip in response to a delay control signal, and thereafter communicating the delayed read command or write command to the second memory chip; and

an address transfer unit transferring an address associated with the read command or the write command to the second memory chip when the command control unit communicates the delayed read command or write command to the second memory chip.

8. The multi-chip memory device of claim 7, wherein the delay control signal is defined in relation to a burst length for data provided by the read operation.

9. The multi-chip memory device of claim 8, wherein either one of the first memory chip or second memory chip comprises a register storing information corresponding to the burst length.

10. The multi-chip memory device of claim 7, wherein the command control unit comprises:

a plurality of delay units delaying the read command or the write command in response to the delay control signal, wherein each delay unit comprises;

a logic operation unit responsive to the delay control signal and the read command or the write command; and

a flip-flop delaying an output signal of the logic operation unit.

11. The multi-chip memory device of claim 7, wherein the address transfer unit communicates the address to the second memory chip in response to the delayed read command.

12. The multi-chip memory device of claim 7, wherein the address transfer unit comprises:

an address storage unit storing the address in response to the read command or the write command applied to the second memory chip; and

an address control unit controlling output of the stored address such that the stored address is communicated to the second memory chip in response to the delayed read command or write command.

13. The multi-chip memory device of claim 1, wherein the transfer memory chip is an interface chip mounted on a printed circuit board (PCB) and transferring externally provided signals to the stacked plurality of memory chips.

14. The multi-chip memory device of claim 1, wherein the transfer memory chip comprises a MUX circuit receiving read data communicated by the signal path.

15. A multi-chip memory device comprising:

a transfer memory chip communicating input/output signals;

a stacked plurality of N memory chips disposed on the transfer memory chip, wherein each one of the N memory chips comprises a memory array having a plurality of M designated banks; and

M signal paths respectively extending upward from the transfer memory chip through the stacked plurality of N memory chips to communicate input/output signals to respective, commonly addressed and vertically aligned banks in each one of the N memory chips to provide read data during a read operation and receive write data during a write operation.

16. The multi-chip memory device of claim 15, wherein each one of the M designated banks is arranged in one of L bank groups, wherein L is less than M.

17. The multi-chip memory device of claim 16, wherein the transfer memory chip comprises a MUX circuit connected via a single connection with multiple signal paths associated with banks in at least one of the L bank groups.

18. A method of fabricating a multi-chip memory device, comprising:

stacking a plurality of N memory chips on a transfer memory chip, wherein each one of the N memory chips comprises a memory array having a plurality of M designated banks; and

providing M signal paths respectively extending upward from the transfer memory chip through the stacked plurality of N memory chips to communicate input/output signals to respective, commonly addressed and vertically aligned banks in each one of the N memory chips to provide read data during a read operation and receive write data during a write operation.

19. The multi-chip memory device of claim 18, wherein each one of the M signal paths is implemented by at least one through silicon via (TSV) formed through a substrate of at least one of the stacked plurality of N memory chips.

20. The multi-chip memory device of claim 18, wherein the input/output signals comprise at least one of a read/write command, an address corresponding to the read/write command, a clock signal associated with the read/write command, and data associated with the read/write command.

21. A method of controlling operation of a multi-chip memory device comprising a stacked plurality of N memory chips, wherein each one of the N memory chips comprises a memory array having a plurality of M designated banks, and M signal paths respectively extending upward from a transfer memory chip through the stacked plurality of N memory chips communicates input/output signals to respective, commonly addressed and vertically aligned banks in each one of the N memory chips, the method comprising:

receiving a read command and a corresponding read address associated with a read operation or receiving a write command and a corresponding write address associated with a write operation in the transfer memory chip;

using a corresponding one of the M signal paths, commonly addressing one bank of the M designated banks in each one of the stacked plurality of N memory chips using the read address or the write address; and

in response to the read command, sequentially outputting to the transfer memory chip a block of read data from each one of the commonly addressed banks in each one of the stacked plurality of N memory chips using the corresponding one of the M signal paths, or in response to the write command sequentially writing a block of write data in each one of the commonly addressed banks in each one of the stacked plurality of N memory chips using the corresponding one of the M signal paths.

22. The method of claim 21, wherein each one of the sequentially output blocks of read data has a size determined in relation to a defined burst length.