MEMORY DEVICE

• US 20090091963A1
• Filed: 10/04/2007
• Published: 04/09/2009
• Est. Priority Date: 10/04/2007
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Patel, Shwetal A.
• Application Number:
  US11/867,208
• Publication Number:
  US 20090091963A1
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A first DRAM device comprises a first input connected to a first trace line to receive an address signal and a second input is connected to receive an operating voltage, such as Vdd. A second DRAM device comprises a first input connected to the first trace line to receive the address signal and a second input to receive the operating voltage. A first signal termination structure is connected to the first trace line, wherein the first signal termination structure is to terminate the first trace line to the operating voltage.

Claims

1. A device comprising:

a first dynamic random access memory (DRAM) comprising a first terminal to receive an address signal, and a second terminal to receive an operating voltage;

a second dynamic random access memory (DRAM) comprising a first terminal to receive the address signal, and a second terminal to receive the operating voltage;

a first trace line connected to the first terminal of the first DRAM, and to the first terminal of the second DRAM;

a first signal termination structure comprising a first terminal connected to the first trace line, and a second terminal; and

a voltage reference bus connected to the second terminal of the first DRAM, to the second terminal of the first DRAM, and to the second terminal of the signal termination structure.

2. The device of claim 1 further comprising:

a printed circuit board having the first DRAM, second DRAM, first trace line, second termination structure, and voltage reference bus disposed thereupon, and further comprising a DIMM connector connected to the first trace line.

3. The device of claim 1 wherein the second terminal of the first DRAM is to receive a Vss operating voltage.

4. The device of claim 1 wherein the second terminal of the first DRAM is to receive a Vdd operating voltage.

5. The device of claim 1 further comprising:

a buffer module comprising a first terminal to receive a signal, and a second terminal connected to the first trace line to provide a buffered representation of the signal.

6. The device of claim 5 further comprising:

a printed circuit board having the first DRAM, second DRAM, first trace line, second termination structure, voltage reference bus, and the buffer disposed thereupon, and further comprising a DIMM connector; and

a second trace line connected to the edge connector, and to the input of the synchronous buffer.

7. The device of claim 5 wherein the buffer module further comprises:

a chip select terminal to receive a chip select signal; and

the second terminal is to provide the buffered representation of the signal in response to the chip select terminal receiving an asserted signal, and the second terminal is to provide a signal having the same voltage as the voltage reference bus in response to the chip select terminal receiving a negated signal.

8. The device of claim 1 wherein:

the first DRAM further comprises a third terminal to receive a control signal;

the second DRAM further comprises a third terminal to receive the control signal;

a second trace line connected to the third terminal of the first DRAM, and to the third terminal of the second DRAM; and

a second signal termination structure comprising a first terminal connected to the second trace line, and a second terminal connected to the voltage reference bus.

9. The device of claim 8 wherein:

the first DRAM further comprises a fourth terminal to receive a command signal;

the second DRAM further comprises a fourth terminal to receive the command signal;

a third trace line connected to the fourth terminal of the first DRAM, and to the fourth terminal of the second DRAM; and

a third signal termination structure comprising a first terminal connected to the third trace line, and a second terminal connected to the voltage reference bus.

10. The device of claim 1 further comprising:

a memory controller comprising an address generation module having a first terminal coupled to the first trace line to provide the address signal in response to the memory controller determining data at the first and second DRAM is being accessed, and to provide the operating voltage in response to the memory controller determining the first and second DRAM are in an idle state.