SOI SUBSTRATE CONTACT WITH EXTENDED SILICIDE AREA

• US 20090093092A1
• Filed: 10/08/2007
• Published: 04/09/2009
• Est. Priority Date: 10/08/2007
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: DANG, DINH, Slinkman, James Albert, Doan, Thai, Levy, Max Gerald, Levy, Jessica Anne, Norris, Alan Frederick
• Application Number:
  US11/868,553
• Publication Number:
  US 20090093092A1
• Time in Patent Office: Days
• US Class Current: 438/151
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Claims

1. A method, comprising:

(a) forming dielectric isolation in an upper silicon layer of a substrate, said substrate comprising a buried oxide layer between said upper silicon layer and a lower silicon layer, said dielectric isolation extending from a top surface of said upper silicon layer to said buried oxide layer, said dielectric isolation surrounding a contact region of said upper silicon layer;

(b) forming an opening extending through said contact region and through said buried oxide layer to said lower silicon layer, portions of said contact region remaining between said opening and said dielectric isolation;

(c) filling said opening with polysilicon to form a polysilicon region;

(d) implanting a dopant of a same dopant type as a dopant type of said lower silicon layer into said polysilicon region and remaining portions of said contact region; and

(e) forming a contiguous metal silicide layer in said remaining portions of said contact region and said polysilicon region, said metal silicide layer extending from a top surface of said polysilicon region into said polysilicon region and extending from a top surface of said remaining portions of said contact region into said remaining portions of said contact region.

2. The method of claim 1, further including:

between (b) and (c) implanting an additional dopant of said same dopant type into a region of said lower silicon layer exposed in a bottom of said opening.

3. The method of claim 2, wherein said additional dopant is implanted at a dose and energy to result in a resistivity of about 0.05 or less at the polysilicon region/lower silicon layer interface.

4. The method of claim 1, further including:

between (c) and (d) removing a layer of said polysilicon region that includes a top surface of said polysilicon region.

5. The method of claim 4, wherein said removing includes performing a wet etch.

6. The method of claim 1, further including:

before (a) forming a pad layer on said top surface of said upper silicon layer;

(b) includes forming said opening through said pad layer; and

before (e) removing said pad layer from said remaining portions of said contact region.

7. The method of claim 1, wherein (c) includes

depositing a layer of polysilicon into said opening and over said top surface of said upper silicon layer and over a top surface of said dielectric isolation;

and

performing a planarization process so a top surface of said polysilicon region is substantially coplanar with a top surface of said dielectric isolation.

8. The method of claim 1, wherein said lower silicon layer and said upper silicon layer are doped P-type.

9. The method of claim 1, wherein said metal silicide layer comprises a metal selected from the group consisting of cobalt, platinum, titanium, tungsten and nickel.

10. The method of claim 1, wherein (b) includes:

forming a photoresist layer over said top surface of said upper silicon layer;

aligning a patterned photomask to said contact region;

exposing said photoresist layer through said patterned photomask;

removing said photoresist from over a region of said contact region; and

performing a reactive ion etch to form said opening.

20. The method of claim 1, wherein (b) includes:

forming a photoresist layer over said top surface of said upper silicon layer;

aligning a patterned photomask to said contact region;

exposing said photoresist layer through said patterned photomask;

removing said photoresist from over a region of said contact region; and

performing a reactive ion etch to form said opening.

11. A method, comprising:

(a) forming dielectric isolation in an upper silicon layer of a substrate, said substrate comprising a buried oxide layer between said upper silicon layer and a lower silicon layer, said dielectric isolation extending from a top surface of said upper silicon layer to said buried oxide layer, said dielectric isolation surrounding a contact region of said upper silicon layer and surrounding a device region of said upper silicon layer;

(b) forming an opening extending through said contact region and through said buried oxide layer to said lower silicon layer, portions of said contact region remaining between said opening and said dielectric isolation;

(c) filling said opening with polysilicon to form a polysilicon region;

(d) forming a gate dielectric layer on top surfaces of said polysilicon region, remaining portions of said contact region and said device region;

(e) forming a gate electrode on said gate dielectric layer;

(f) implanting a dopant of a same dopant type as a dopant type of said lower silicon layer into said polysilicon region, remaining portions of said contact region and source/drain regions in said device region;

said source/drain regions on opposite sides of said gate electrode not covered by said gate electrode;

(g) removing said gate dielectric layer from over said polysilicon region, remaining portions of said contact region and said source/drain regions; and

(h) forming metal silicide layers in said remaining portions of said contact region, said polysilicon region and said source/drain regions, said metal silicide layers extending from respective top surfaces of said polysilicon region into said polysilicon region, of said remaining portions of said contact region into said remaining portions of said contact region and of said source/drain regions into said source/drain regions, said metal silicide layers in said remaining portions of said contact region and said polysilicon region being contiguous.

12. The method of claim 11, further including:

between (b) and (c) implanting an additional dopant of said same dopant type into a region of said lower silicon layer exposed in a bottom of said opening.

13. The method of claim 12, wherein said additional dopant is implanted at a dose and energy to result in a resistivity of about 0.05 or less at the polysilicon region/lower silicon layer interface.

14. The method of claim 11, further including:

between (c) and (d) removing a layer of said polysilicon region from a top surface of said polysilicon region.

15. The method of claim 14, wherein said removing includes performing a wet etch.

16. The method of claim 11, further including:

before (a) forming a pad layer on said top surface of said upper silicon layer;

(b) includes forming said opening through said pad layer; and

between (c) and (d) removing said pad layer from said remaining portions of said contact region and from said device region.

17. The method of claim 11, wherein (c) includes

depositing a layer of polysilicon into said opening and over said top surface of said upper silicon layer and over a top surface of said dielectric isolation;

and

performing a chemical-mechanical polish so a top surface of said polysilicon region is substantially coplanar with a top surface of said dielectric isolation.

18. The method of claim 11, wherein said lower silicon layer and said upper silicon layer are doped P-type.

19. The method of claim 11, wherein said metal silicide layers comprises a metal selected from the group consisting of cobalt, platinum, titanium, tungsten and nickel.