Selective Formation of Silicon Carbon Epitaxial Layer

• US 20090093094A1
• Filed: 10/05/2007
• Published: 04/09/2009
• Est. Priority Date: 10/05/2007
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Ye, Zhiyuan, Kim, Yihwan, Chopra, Saurabh, Lam, Andrew
• Granted Patent: US 7,776,698 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Methods for formation of epitaxial layers containing n-doped silicon are disclosed, including methods for the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. Formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source at a first temperature and pressure and then exposing the substrate to an etchant at a second higher temperature and a higher pressure than during deposition.

Claims

1. A method for epitaxially forming a silicon-carbon film on a substrate surface, comprising:

placing a substrate including a monocrystalline surface and secondary surfaces into a process chamber;

exposing the substrate to deposition gases comprising a silicon source, a carbon source and an n-type dopant at a deposition temperature of less than about 600°

C. and a deposition pressure; and

exposing the substrate to an etching gas comprising hydrogen chloride an etching temperature exceeding about 600°

C. and an etching pressure at least about 10 times the deposition pressure and exceeding about 100 Torr, the method resulting in selective deposition of heavily doped n-type epitaxy on the monocrystalline surface.

2. The method of claim 1, wherein the dopant comprises one or more of phosphorus and arsenic sources.

3. The method of claim 2, wherein the phosphorus source comprises phosphine and the arsenic source comprises arsine.

4. The method of claim 2, wherein the etching gas comprises only hydrogen chloride.

5. The method of claim 4, wherein the hydrogen chloride is delivered to the chamber from a hydrogen chloride source gas.

6. The method of claim 4, wherein the hydrogen chloride is formed in the chamber upon mixing hydrogen and chlorine source gases in the chamber.

7. The method of claim 4, wherein the silicon source is selected from a mixture of monosilane and a higher order silane.

8. The method of claim 7, wherein the higher order silane is selected from disilane and neo-pentasilane.

9. The method of claim 2, wherein the dopant is present in the n-type epitaxy at a level of at least about 2 ×

10²⁰ atoms/cm³

10. The method of claim 9, wherein the dopant level is at least about 5 ×

10²⁰ atoms/cm³.

11. The method of claim 8, wherein the deposition temperature is in the range of about 575°

C. and below about 600°

C.

12. The method of claim 11, wherein the etching temperature is in the range of above about 600°

C. and below about 650°

C.

13. The method of claim 12, wherein dichlorosilane is flowed during deposition.

14. The method of claim 12, wherein the carbon source comprises methylsilane.

15. The method of claim 12, wherein hydrogen chloride is additionally flowed during deposition.

16. The method of claim 1, wherein the epitaxial film is formed during a fabrication step of a transistor manufacturing process, and the method further comprises:

forming a gate dielectric on the substrate;

forming a gate electrode on the gate dielectric; and

forming source/drain regions on the substrate on opposite sides of the gate electrode and defining a channel region between the source/drain regions.

17. The method of claim 12, wherein the epitaxial film is formed during a fabrication step of a transistor manufacturing process, and the method further comprises:

forming a gate dielectric on the substrate;

forming a gate electrode on the gate dielectric; and

forming source/drain regions on the substrate on opposite sides of the gate electrode and defining a channel region between the source/drain regions.

18. The method of claim 1, wherein the etching pressure is at least about 30 times the deposition pressure.

19. The method of claim 1 wherein the deposited n-type epitaxy has a carbon concentration of greater than 1%.

20. The method of claim 19 wherein the deposited n-type epitaxy has a carbon concentration of greater than 1.5%.