Data processing apparatus and method employing multiple register sets

• US 20090094439A1
• Filed: 05/11/2005
• Published: 04/09/2009
• Est. Priority Date: 05/11/2005
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Gilday, David Michael, Kershaw, Danel, Biles, Stuart David, Mansell, David Hennah
• Granted Patent: US 8,041,930 B2
• Time in Patent Office: Days
• US Class Current: 712/200
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A data processing apparatus and method employing multiple register sets is disclosed. The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group. This has been found to provide a particularly efficient use of the registers within the data processing apparatus.

Claims

1. A data processing apparatus, comprising:

processing logic operable to perform data processing operations;

a register bank operable to store data associated with the processing logic, the register bank having at least one register group, each register group comprising a plurality of register sets;

the processing logic having an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic, said single execution thread associated with said second operating state requiring more architectural state than is required for any independent execution thread associated with said first operating state; and

control logic operable to control how the register sets of each register group are used dependent on the operating state associated with that register group.

2. A data processing apparatus as claimed in claim 1, wherein the register bank comprises a single register group.

3. A data processing apparatus as claimed in claim 1, wherein each register group comprises a pair of register sets.

4. A data processing apparatus as claimed in claim 3, wherein in the second operating state the processing logic is selectively operable in either a secure domain or a non-secure domain.

5. A data processing apparatus as claimed in claim 4, wherein in the second operating state, a first register set of the associated pair of register sets contains a first subset of registers that are used when operating in the secure domain or the non-secure domain and a second subset of registers that are only used when operating in one of the secure or non-secure domains, when the processing logic is operating in the other of the secure or non-secure domains a number of registers in a second register set of that associated pair of register sets being used instead of the second subset of registers.

6. A data processing apparatus as claimed in claim 1, wherein each register set in the register bank comprises working registers operable to store data for manipulation by the processing logic and/or control registers operable to store one or more control parameters for controlling operation of the data processing apparatus.

7. A data processing apparatus as claimed in claim 1, further comprising:

a control value register operable to store for each register group an operating state control value identifying the operating state associated with that register group, the control logic being responsive to each operating state control value to control how the register sets of the associated register group are used.

8. A data processing apparatus as claimed in claim 7, wherein the control logic comprises a number of control units, one control unit being provided for each register group, each control unit being operable to receive the operating state control value for the associated register group, a thread control value indicating for the first operating state which execution thread is being executed by the processing logic, and a non-secure control value indicating for the second operating state whether the processing logic is operating in either the secure domain or the non-secure domain, and to control in dependence on these control values how the register sets of that associated register group are used.

9. A data processing apparatus as claimed in claim 1, wherein in the first operating state each register set of at least one register group has associated therewith a security value indicating whether the associated execution thread is executing in the secure domain or the non-secure domain.

10. A data processing apparatus, comprising:

processing means for performing data processing operations;

register bank means for storing data associated with the processing means, the register bank means having at least one register group, each register group comprising a plurality of register sets;

the processing means having an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing means, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing means, said single execution thread associated with said second operating state requiring more architectural state than is required for any independent execution thread associated with said first operating state; and

control means for controlling how the register sets of each register group are used dependent on the operating state associated with that register group.

11. A method of operating a data processing apparatus having processing logic for performing data processing operations, and a register bank for storing data associated with the processing logic, the register bank having at least one register group, each register group comprising a plurality of register sets, the method comprising the steps of:

associating an operating state with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic, said single execution thread associated with said second operating state requiring more architectural state than is required for any independent execution thread associated with said first operating state; and

controlling how the register sets of each register group are used dependent on the operating state associated with that register group.