DRAM CELLS WITH VERTICAL TRANSISTORS
First Claim
1. A transistor comprising:
- a semiconductor substrate;
a U-shaped structure comprising a first pillar, a second pillar and a channel base segment connecting bottom portions of the first and second pillars, the U-shaped structure extending from the semiconductor substrate and comprising a first U-shaped sidewall and a second U-shaped sidewall on opposite sides connected by facing inner walls of the first and second pillars, an upper surface of the channel base segment and end walls of the first and second pillars;
a drain region formed at a top of the first pillar;
a source region formed at a top of the second pillar;
a first U-shaped channel formed along the first U-shaped sidewall, wherein the first U-shaped channel comprises a horizontal portion along the channel base segment and vertical portions along the pillars; and
a first gate line facing the first U-shaped sidewall.
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Accused Products
Abstract
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.
110 Citations
20 Claims
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1. A transistor comprising:
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a semiconductor substrate; a U-shaped structure comprising a first pillar, a second pillar and a channel base segment connecting bottom portions of the first and second pillars, the U-shaped structure extending from the semiconductor substrate and comprising a first U-shaped sidewall and a second U-shaped sidewall on opposite sides connected by facing inner walls of the first and second pillars, an upper surface of the channel base segment and end walls of the first and second pillars; a drain region formed at a top of the first pillar; a source region formed at a top of the second pillar; a first U-shaped channel formed along the first U-shaped sidewall, wherein the first U-shaped channel comprises a horizontal portion along the channel base segment and vertical portions along the pillars; and a first gate line facing the first U-shaped sidewall. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A transistor array comprising:
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a column of U-shaped structures each comprising a first pillar, a second pillar and a channel base segment connecting bottom portions of the first and second pillars, each U-shaped structure extending from the semiconductor substrate and comprising a first U-shaped sidewall and a second U-shaped sidewall on opposite sides connected by facing inner walls of the first and second pillars, an upper surface of the channel base segment and end walls of the first and second pillars; a drain region formed at a top of the first pillar of each U-shaped structure; a source region formed at a top of the second pillar of each U-shaped structure; a first U-shaped channel formed along the first U-shaped sidewall in each U-shaped structure, wherein each U-shaped channel comprises a horizontal portion along the channel base segment and vertical portions along the first and second pillars; and a first wordline formed along and facing the first U-shaped sidewalls of the column. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification