NONVOLATILE MEMORIES WHICH COMBINE A DIELECTRIC, CHARGE-TRAPPING LAYER WITH A FLOATING GATE

• US 20090096009A1
• Filed: 10/16/2007
• Published: 04/16/2009
• Est. Priority Date: 10/16/2007
• Status: Abandoned Application

• Current Assignee: Promos Technologies Pte Ltd (ProMOS Technologies, Inc.)
• Original Assignee: Promos Technologies Pte Ltd (ProMOS Technologies, Inc.)
• Inventors: Chen, Ching-Hwa, Dong, Zhong, Chen, Chiliang
• Application Number:
  US11/872,998
• Publication Number:
  US 20090096009A1
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A nonvolatile memory cell stores at least 50% of the charge in a dielectric, charge-trapping layer (160) and at least 20% of the charge in a floating gate (170). The floating gate is at most 20 nm thick.

Claims

1. An integrated circuit comprising a nonvolatile memory cell comprising:

a semiconductor region for providing electric charge for altering a state of the nonvolatile memory cell;

a dielectric, charge-trapping layer for trapping and storing electric charge to define the state of the nonvolatile memory cell;

a tunnel dielectric separating the semiconductor region from the dielectric, charge-trapping layer; and

a floating gate separated from the semiconductor region by the tunnel dielectric and the dielectric, charge-trapping layer, for storing charge to define the state of the nonvolatile memory cell, the floating gate being a layer at most 20 nm thick.

2. The integrated circuit of claim 1 wherein the memory cell has a state defined by a non-zero charge stored in the dielectric, charge-trapping layer and the floating gate, with at least 50% of the non-zero charge stored in the dielectric, charge-trapping layer and at least 20% of the non-zero charge stored in the floating gate.

3. The integrated circuit of claim 1 further comprising:

a control gate separated from the semiconductor region by the floating gate, the dielectric, charge-trapping layer and the tunnel dielectric; and

a blocking dielectric separating the floating gate from the control gate.

4. The integrated circuit of claim 1 wherein the semiconductor region comprises a channel region and source/drain regions of the memory cell.

5. The integrated circuit of claim 1 wherein the dielectric, charge-trapping layer is embedded with conductive or semiconductor particles.

6. The integrated circuit of claim 1 wherein the floating gate is at least 1 nm thick.

7. An integrated circuit comprising a nonvolatile memory cell comprising:

a dielectric, charge-trapping layer, for storing at least part of a charge defining a state of the nonvolatile memory cell; and

a floating gate overlying and physically contacting the dielectric, charge-trapping layer;

wherein the memory cell has a state defined by a non-zero charge stored in the dielectric, charge-trapping layer and the floating gate, with at least 50% of the non-zero charge stored in the dielectric, charge-trapping layer and at least 20% of the non-zero charge stored in the floating gate.

8. The integrated circuit of claim 7 further comprising:

a semiconductor region for providing electric charge for altering the memory cell'"'"'s state; and

a tunnel dielectric separating the semiconductor region from the dielectric, charge-trapping layer.

9. The integrated circuit of claim 8 further comprising a control gate separated from the semiconductor region by the floating gate, the dielectric, charge-trapping layer and the tunnel dielectric;

and

a blocking dielectric separating the floating gate from the control gate.

10. A method for fabricating an integrated circuit comprising a nonvolatile memory cell, the method comprising:

forming a tunnel dielectric for the nonvolatile memory cell on a semiconductor region providing a portion of the nonvolatile memory cell;

forming a dielectric, charge-trapping layer for the nonvolatile memory cell on the tunnel dielectric; and

forming a floating gate for the nonvolatile memory cell on the charge-trapping layer, the floating gate being at most 20 nm thick.

11. The method of claim 10 wherein the memory cell has a state defined by a non-zero charge stored in the dielectric, charge-trapping layer and the floating gate, with at least 50% of the non-zero charge stored in the dielectric, charge-trapping layer and at least 20% of the non-zero charge stored in the floating gate.

12. The method of claim 10 further comprising forming a control gate for the nonvolatile memory cell over the floating gate.

13. The method of claim 10 wherein the floating gate is at least 1 nm thick.

14. The method of claim 13 wherein the floating gate is made of doped polysilicon.