METHOD FOR PRODUCING A THIN SEMICONDUCTOR CHIP COMPRISING AN INTEGRATED CIRCUIT
First Claim
Patent Images
1. A method for producing a thin semiconductor chip comprising an integrated circuit, the method comprising the steps of:
- providing a semiconductor wafer having a first and a second surface, the semi-conductor wafer being composed of p-doped silicon in the region of the first surface, defining at least one wafer section in the region of the first surface, converting the p-doped silicon in the region of the defined wafer section into porous silicon having a plurality of pores by means of an anodic etching process, the porous silicon comprising an upper layer at the first surface and a lower layer below the upper layer,producing a wafer cavity below the at least one defined wafer section by thermally treating the porous silicon such that the pores of the upper layer are substantially closed by material from the lower layer,producing a circuit structure in the at least one defined wafer section, andreleasing the defined wafer section from the semiconductor wafer,wherein the wafer section is freed in a first process sequence such that it is held only via web-like connections on the remaining semiconductor wafer, andwherein the web-like connections are severed in a second process sequence.
1 Assignment
0 Petitions
Accused Products
Abstract
In a method for producing a thin film chip including an integrated circuit, a semi-conductor wafer having a first surface is provided. At least one cavity is produced under a defined section of the first surface by means of porous silicon. A circuit structure is produced in the defined section. The defined wafer section is subsequently released from the semiconductor wafer by severing local web-like connections, which hold the wafer section above the cavity and on the remaining semiconductor wafer.
15 Citations
16 Claims
-
1. A method for producing a thin semiconductor chip comprising an integrated circuit, the method comprising the steps of:
-
providing a semiconductor wafer having a first and a second surface, the semi-conductor wafer being composed of p-doped silicon in the region of the first surface, defining at least one wafer section in the region of the first surface, converting the p-doped silicon in the region of the defined wafer section into porous silicon having a plurality of pores by means of an anodic etching process, the porous silicon comprising an upper layer at the first surface and a lower layer below the upper layer, producing a wafer cavity below the at least one defined wafer section by thermally treating the porous silicon such that the pores of the upper layer are substantially closed by material from the lower layer, producing a circuit structure in the at least one defined wafer section, and releasing the defined wafer section from the semiconductor wafer, wherein the wafer section is freed in a first process sequence such that it is held only via web-like connections on the remaining semiconductor wafer, and wherein the web-like connections are severed in a second process sequence. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. An integrated circuit chip comprising a circuit structure formed in a semi-conductor material having at least a first material layer and a second material layer, wherein the first and the second material layers are arranged one above another, wherein the circuit structure is essentially formed in the first material layer, and wherein residues of severed web-like connections are arranged in the region of the second material layer, wherein the second material layer contains p-doped porous silicon which has been subjected to a thermal treatment.
Specification