Method of inspecting semiconductor circuit having logic circuit as inspection circuit

• US 20090096476A1
• Filed: 10/09/2008
• Published: 04/16/2009
• Est. Priority Date: 10/10/2007
• Status: Abandoned Application

• Current Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Koyama, Takahiro
• Application Number:
  US12/285,597
• Publication Number:
  US 20090096476A1
• Time in Patent Office: Days
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer

Abstract

A semiconductor circuit includes an inspection circuit for inspecting terminal open of the semiconductor circuit. The semiconductor circuit has a plurality of input terminals. The semiconductor circuit includes an input circuit portion connected to the plurality of input terminals. The inspection circuit includes a logic circuit, supplied with a plurality of input signals from the input circuit portion, for performing a predetermined logic operation to the plurality of input signals to produce a logic operation result. Whereby the semiconductor circuit enables to decide the presence or absence of the terminal open on the basis of the logic operation result.

Claims

1. A semiconductor circuit comprising an inspection circuit for inspecting terminal open of said semiconductor circuit, said semiconductor circuit having a plurality of input terminals, wherein

said semiconductor circuit comprises an input circuit portion connected to said plurality of input terminals,

said inspection circuit comprising a logic circuit, supplied with a plurality of input signals from said input circuit portion, for performing a predetermined logic operation to said plurality of input signals to produce a logic operation result, whereby enabling to decide the presence or absence of said terminal open on the basis of the logic operation result.

2. The semiconductor circuit as claimed in claim 1, wherein said logic circuit comprises at least two different logic circuit portions.

3. The semiconductor circuit as claimed in claim 2, wherein said logic circuit comprises an OR circuit portion and an AND circuit portion as the at least two different logic circuit portions,

said OR circuit portion being configured to produce a signal of a logic “

L”

level if there is nothing wrong with said plurality of input terminals when all of said plurality of input terminals are supplied with the logic “

L”

level,

said AND circuit portion being configured to produce a signal of a logic “

H”

level if there is nothing wrong with said plurality of input terminals when all of said plurality of input terminals are supplied with the logic “

H”

level.

4. The semiconductor circuit as claimed in claim 3, wherein said OR circuit portion comprises a plurality of 2-input OR circuits which are cascade connected to said plurality of input terminals through said input circuit portion,

said AND circuit portion comprising a plurality of 2-input AND circuits which are cascade connected to said plurality of input terminals through said input circuit portion.

5. A semiconductor circuit as claimed in claim 3, wherein said semiconductor circuit has first and second output terminals, said semiconductor circuit comprising an output circuit portion connected to said first and said second output terminals,

wherein said inspection circuit further comprises an inverter for inverting an output signal of said OR circuit portion to supply an inverted signal to said first output terminal through said output circuit portion,

wherein an output signal of said AND circuit is supplied to said second output terminal through said output circuit portion.

6. A method of inspecting a terminal open of the semiconductor circuit as claimed in claim 3, said method comprising:

supplying all of said plurality of input terminals with one of the logic “

H”

level and the logic “

L”

level; and

supplying all of said plurality of input terminals with another of the logic “

H”

level and the logic “

L”

level,

whereby enabling to decide the presence or absence of the terminal open of said semiconductor circuit in accordance with a level of an output signal of said logic circuit.

7. A method of inspecting terminal opens of a semiconductor device comprising a plurality of semiconductor circuits each as claimed in claim 3 that are arranged in parallel, said method comprising:

connecting said plurality of input terminals of all of said semiconductor circuits in common, respectively;

supplying all of said plurality of input terminals with one of the logic “

H”

level and the logic “

L”

level; and

supplying all of said plurality of input terminals with another of the logic “

H”

level and the logic “

L”

level,

whereby enabling to decide the presence or absence of the terminal opens of said semiconductor device for said semiconductor circuits individually in accordance with a level of an output signal of said logic circuit.

8. The semiconductor circuit as claimed in claim 3, wherein said inspection circuit further comprises a plurality of inverters for alternately inverting input signals supplied from said plurality of input terminals through said input circuit portion.

9. A method of inspecting a terminal open of the semiconductor circuit as claimed in claim 8, wherein said method comprising:

supplying said plurality of input terminals with a bit parallel first input signal where logic levels are in turn inverted; and

supplying said plurality of input terminals with a bit parallel second input signal obtained by inverting the bit parallel first input signal,

whereby enabling to decide the presence or absence of the terminal open of said semiconductor circuit in accordance with a level of an output signal of said logic circuit.

10. A method of inspecting terminal opens of a semiconductor device comprising a plurality of semiconductor circuits each as claimed in claim 8 that are arranged in parallel, said method comprising:

connecting said plurality of input terminals of all of said semiconductor circuits in common, respectively;

supplying said plurality of input terminals with a bit parallel first input signal where logic levels are in turn inverted; and

supplying said plurality of input terminals with a bit parallel second input signal obtained by inverting the bit parallel first input signal,

whereby enabling to decide the presence or absence of the terminal opens of said semiconductor device for said semiconductor circuits individually in accordance with a level of an output signal of said logic circuit.