Memory Device Receiver

• US 20090097338A1
• Filed: 10/24/2008
• Published: 04/16/2009
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: Carl Werner, Mark Horowitz, Pak Chau, Scott Best, Stefanos Sidiropoulos
• Original Assignee: Carl Werner, Mark Horowitz, Pak Chau, Scott Best, Stefanos Sidiropoulos
• Inventors: Sidiropoulos, Stefanos, Horowitz, Mark, Best, Scott, Chau, Pak, Werner, Carl
• Granted Patent: US 7,859,436 B2
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4902 : Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 7/0331 : with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

A memory device includes a receiver to receive an input data signal and to create an output signal corresponding to the present received data signal and a voltage representative of a signal sampled earlier in time.

Claims

1. A memory device comprising:

a receiver to receive an input data signal and to create an output signal corresponding to the present received data signal and a voltage representative of a signal sampled earlier in time.

2. The memory device of claim 1, wherein the voltage is weighted by a control voltage.

3. The memory device of claim 2, further comprising:

a register to store the control voltage.

5. The memory device of claim 1, wherein the voltage is weighted by a control voltage.

6. The memory device of claim 2, further comprising:

a register to store the control voltage.

4. A memory device comprising:

a receiver to receive an input data signal and to create an output signal corresponding to the present received data signal and a voltage representative of a previously received data signal.

7. A memory system comprising:

a memory controller; and

one or more memory devices, at least one memory device comprising;

receiver to receive an input data signal and to create an output signal corresponding to the present received data signal and a voltage representative of a signal sampled earlier in time.

8. The memory system of claim 7, wherein the voltage is weighted by a control voltage.

9. The memory system of claim 8, wherein the at least one memory device further comprises:

a register to store the control voltage.

10. An integrated circuit memory device comprising:

even and odd receivers having respective inputs to receive data bits from adjacent data cycles and respective output nodes; and

an equalization circuit coupled to the respective output nodes to compensate the received data bits based on respective values of previous data bits.