METHOD AND SYSTEM OF DETECTING AND LOCKING TO MULTI-STANDARD VIDEO STREAMS

• US 20090097607A1
• Filed: 10/12/2007
• Published: 04/16/2009
• Est. Priority Date: 10/12/2007
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Slayton, Gary E.
• Granted Patent: US 7,940,879 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03D 3/241 the oscillator being part of a phase locked loop

Abstract

A video processing system includes a video detection circuit for determining the clock frequency of an incoming video signal. Using the determined clock frequency, adjustments are made in a phase lock loop to enable a quick lock onto the clock frequency of the incoming video signal.

Claims

1. A video processing circuit comprising:

a incoming video circuit for receiving an incoming video signal;

a phase lock loop circuit for receiving a signal representing the frequency of said incoming video signal and providing an output signal related to the frequency of said incoming video signal; and

a determining and setting circuit for determining a clock frequency of said incoming video signal and responsive thereto for determining and setting operating parameters for said phase lock loop circuit.

2. The video processing circuit of claim 1, wherein said determining and setting circuit further comprises:

a frequency counter circuit for determining a clock frequency of the incoming video signal, said frequency counter circuit coupled to said incoming video circuit.

3. The video processing circuit of claim 2, wherein said determining and setting circuit further comprises:

a decision logic circuit, coupled to and configured to receive input from said frequency counter circuit, configured to determine filter parameters for a filter circuit in said phase lock loop circuit.

4. The video processing circuit of claim 3, wherein said decision logic circuit is configured to determine a divider value for at least one divider provided in said phase lock loop circuit.

5. The video processing circuit of claim 3, wherein said phase lock loop circuit comprises:

a phase comparator circuit for comparing two incoming signals and proving an output indicating the results of said comparison; and

an oscillator circuit for providing a clock reference signal to a downstream circuit and to said phase comparator circuit as one of said two incoming signals.

6. The video processing circuit of claim 5, further comprising:

said filter circuit for filtering a signal being provided to said oscillator circuit from said phase comparator circuit, said filter circuit being coupled in between said phase comparator circuit and said oscillator circuit, said filter circuit coupled to said decision logic circuit for receiving filter parameters.

7. The video processing circuit of claim 6, further comprising:

a first divide circuit for dividing a signal provided to said phase comparator circuit from said oscillator circuit, said first divide circuit coupled for receiving a first divisor parameter from said decision logic circuit,

where said decision logic circuit is configured to determine a first divisor parameters for said first divide circuit.

8. The video processing circuit of claim 7, further comprising:

a second divide circuit for dividing a signal provided to said phase comparator circuit from said incoming video circuit, said second divide circuit coupled for receiving a second divisor parameter from said decision logic circuit,

where said decision logic circuit is configured to determine a second divisor parameters for said second divide circuit.

9. The video processing circuit of claim 6, wherein said filter is a low pass filter.

10. The video processing circuit of claim 6, wherein said filter is a lead/lag filter.

11. A method of processing a video signal, said method comprising:

counting a frequency representing a frequency of an incoming video signal;

determining a clock frequency of said incoming video signal;

adjusting parameters of a first signal provided to a phase lock loop circuit, which locks to a signal representing said incoming video signal based on the determined clock frequency; and

providing a second signal by said phase lock loop circuit a process clock frequency for use in processing said incoming video signal, said process clock frequency related to said frequency of said incoming video signal.

12. The method of claim 11, further comprising the step of:

adjusting parameters of said second signal based on the determined clock frequency.

13. The method of claim 12, wherein said first signal is said frequency representing a frequency of an incoming video signal is adjusted by a filter.

14. The method of claim 13, wherein said second signal is an output of a controlled oscillator.

15. The method of claim 12, further comprising the step of:

comparing by said phase lock loop said first and second signals and outputting a result of said comparing;

adjusting said result by a third signal based on said determined clock frequency of said incoming video signal; and

providing said adjusted result to a controlled oscillator.

16. A video processing circuit for processing an incoming video stream, comprising:

an incoming video signal circuit for receiving an incoming video signal;

a frequency counter circuit for determining a clock frequency of said incoming video signal and determining a video format based on the determined clock frequency, said frequency counter comprises;

a period counter circuit for counting a period representing time between a sync signals of said incoming video signal,

a timeout circuit for monitoring elapsed time between successive sync signals and providing a hold signal when a sync signal is detected as missing; and

latch circuit for holding a signal from said period counter, said latch circuit coupled to and being configured to receive said sync signals, signals from said period counter circuit and signals from said timeout circuit, said latch circuit being reset with a new signal from said period counter whenever a sync signal is received except when a hold signal is received from said timeout circuit.

17. The video processing circuit of claim 16, further comprising:

a phase lock loop circuit for receiving a signal representing the frequency of said incoming video signal from said incoming video signal circuit and providing an output signal related to the frequency of said incoming video signal

18. The video processing circuit of claim 17, further comprising:

a decision logic circuit coupled to and configured to receive input from said frequency counter circuit, said decision logic circuit configured to determine filter parameters that corresponds to the determined video format.

19. The video processing circuit of claim 18, wherein said decision logic circuit is configured to determine first divider parameters that correspond to the video format.

20. The video processing circuit of claim 19, wherein said decision logic circuit is configured to determine second divider parameters that correspond to the video format.

21. The video processing circuit of claim 17, wherein said video detection circuit further comprises:

an oscillator; and

a filter coupled to and being configured to receive filter parameters input from said decision logic circuit, said filter being configured to process a signal received from said incoming video signal circuit, said filter coupled to and being configured to provide output to said oscillator based on said input from said decision logic circuit.

22. The video processing system of claim 21, wherein said filter is a low pass filter.

23. The video processing system of claim 22, wherein said filter is a lead/lag filter.

24. The video processing system of claim 19, wherein said video detection circuit further comprises:

a first divide circuit, coupled to and being configured to receive input from said controlled oscillator, said first divide circuit coupled to and being configured to receive input about a divider from said decision logic circuit, said first divide circuit coupled to and being configured to provide output to said phase comparator, said first divide circuit being configured to process a signal received from said controlled oscillator based on input from said decision logic circuit and providing a result of said determination to said phase comparator.