Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein

• US 20090098706A1
• Filed: 10/12/2007
• Published: 04/16/2009
• Est. Priority Date: 10/12/2007
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Inventors: Widodo, Johnny, Lun, Zhao, Kim, Jun-jung, Zuo, Biao, Wille, William C., Kim, Joo-chan, Park, Jae-eon, Conti, Richard Anthony
• Granted Patent: US 7,838,390 B2
• Time in Patent Office: Days
• US Class Current: 438/438
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×10¹⁴ ions/cm². The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.

Claims

1. A method of forming an integrated circuit device, comprising:

forming a trench in a surface of semiconductor substrate;

filling the trench with an electrically insulating region having a seam therein by depositing an electrically insulating layer on sidewalls and a bottom of the trench;

implanting curing ions into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein; and

annealing the electrically insulating region and curing ions therein at a sufficient temperature and for a sufficient duration to increase a degree of atomic order therein.

2. The method of claim 1, wherein the curing ions are ions selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe).

3. The method of claim 1, wherein said implanting step is preceded by a step of planarizing a surface of the electrically insulating region;

and wherein said implanting step comprises implanting curing ions into the planarized surface of the electrically insulating region.

4. The method of claim 1, wherein said annealing step comprises annealing the electrically insulating region at a temperature of at least about 600°

C.

5. The method of claim 4, wherein said annealing step comprises annealing the electrically insulating region at a temperature of about 1050°

C. for about 30 minutes.

6. The method of claim 1, wherein said step of implanting curing ions into the electrically insulating region comprises implanting germanium ions at an energy of at least about 80 KeV and at a dose of at least about 5×

10¹⁴ ions/cm².

7. The method of claim 3, wherein said planarizing step is preceded by a step of annealing the electrically insulating region to increase a degree of atomic order therein.

8. The method of claim 1, wherein the electrically insulating layer is a HARP O₃-TEOS layer.

9. A method of forming an integrated circuit device, comprising:

forming a trench in a surface of semiconductor substrate;

thermally oxidizing sidewalls of the trench to define a thermal oxide layer thereon;

depositing a silicon nitride layer on the thermal oxide layer;

filling the trench with an electrically insulating region by depositing an electrically insulating layer on the silicon nitride layer;

planarizing the electrically insulating region for a sufficient duration to expose portions of the silicon nitride layer extending outside the trench;

implanting curing ions into the planarized electrically insulating region at a sufficient energy and dose to reduce a degree of atomig order therein; and

annealing the electrically insulating region at a sufficient temperature and for a sufficient duration to redistribute the curing ions and increase a degree of atomic order within the electrically insulating region.

10. The method of claim 9, wherein said implanting step comprises implanting curing ions selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe).

11. The method of claim 9, wherein said annealing step is followed by a step of removing at least a portion of the silicon nitride layer from the semiconductor substrate.

12. The method of claim 9, wherein the curing ions are implanted at a sufficient energy and dose to convert at least a portion of the electrically insulating region to an amorphous electrically insulating region.

13. The method of claim 12, wherein said annealing step comprises annealing the electrically insulating region at a sufficient temperature and for a sufficient duration to at least partially crystallize at least a portion of the amorphous electrically insulating region.