METHOD FOR PRODUCING A THIN CHIP COMPRISING AN INTEGRATED CIRCUIT

• US 20090098708A1
• Filed: 09/11/2008
• Published: 04/16/2009
• Est. Priority Date: 03/14/2006
• Status: Active Grant

• Current Assignee: Institut fuer Mikroelektronik Stuttgart
• Original Assignee: Institut fuer Mikroelektronik Stuttgart
• Inventors: ZIMMERMANN, Martin, APPEL, Wolfgang, BURGHARTZ, Joachim N.
• Granted Patent: US 8,466,037 B2
• Time in Patent Office: Days
• US Class Current: 438/458
• CPC Class Codes: H01L 21/02002 Preparing wafers
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off

Abstract

In a method for producing a very thin chip including an integrated circuit, a circuit structure is produced in a defined section of a semiconductor wafer. The defined wafer section is subsequently released from the semiconductor wafer. For this purpose, the wafer section is firstly freed such that it is held only via local web-like connections on the remaining semiconductor wafer, which web-like connections are arranged at a lateral periphery of the wafer section. The web-like connections are subsequently severed.

Claims

1. A method for producing a thin film chip comprising an integrated circuit, the method comprising the steps of:

providing a semiconductor wafer having a top side and a bottom side,

producing a plurality of hidden wafer cavities near the top side,

defining a plurality of wafer sections at the top side, with each wafer section having a lateral periphery and lying above a hidden wafer cavity,

producing at least one circuit structure in at least one defined wafer section, and

separating the defined wafer section from the semiconductor wafer,

wherein the step of separating includes a first process sequence, wherein trenches down to the hidden cavities are produced such that the defined wafer section is held on the semiconductor wafer only via local web-like connections, which are arranged at the lateral periphery, and

wherein the web-like connections are severed in a second process sequence.

2. The method of claim 1, wherein the web-like connections are broken by means of a pressure applied to the defined wafer section from above.

3. The method of claim 1, wherein the semiconductor wafer comprises a first semiconductor material at the top side and a second semiconductor material at the bottom side, and the step of producing the wafer cavities comprises the steps of:

producing a plurality of porous regions in the first semiconductor material, and

producing a cover layer on the top side, which covers the porous regions.

4. The method of claim 3, wherein each porous region is produced with a large-pored lower layer and a fine-pored upper layer.

5. The method of claim 4, wherein the wafer is heated after the porous regions have been produced, in order to produce the cover layer by thermically induced reflow of semiconductor material from the large-pored lower layer to the fine-pored upper layer.

6. The method of claim 4, wherein an epitaxial layer is grown at the top side in order to produce the cover layer.

20. The method of claim 1, wherein the semiconductor wafer comprises a crystal lattice having a [100] direction and a [110] direction, wherein the defined wafer section is arranged parallel to the [100] direction or parallel to the [110] direction, and wherein the web-like connections are arranged at comers or at lateral edges of the defined wafer section.

7. A method for producing a thin film chip comprising an integrated circuit, the method comprising the steps of:

providing a semiconductor wafer having a top surface and a bottom surface,

defining a plurality of wafer sections at the top surface, with each wafer section having a lateral periphery,

producing at least one circuit structure in at least one defined wafer section, and

releasing the defined wafer section from the semiconductor wafer,

wherein the defined wafer section is freed in a first process sequence such that the wafer section is held on the remaining semiconductor wafer via local web-like connections, which are arranged at the lateral periphery, and

wherein the web-like connections are severed in a second process sequence.

8. The method of claim 7, wherein the web-like connections are broken by means of a pressure applied to the defined wafer section from the top surface.

9. The method of claim 7, wherein the first process sequence comprises a step of producing a closed wafer cavity below the defined wafer section.

10. The method of claim 9, wherein the circuit structure is produced above the closed wafer cavity.

11. The method of claim 9, wherein the step of producing the closed wafer cavity comprises the following steps:

providing the semiconductor wafer having the top side composed of a first semiconductor material,

producing a plurality of porous regions in the first semiconductor material, wherein each porous region laterally extends below and matches a defined wafer section, and

producing a cover layer on the top side, which covers the porous regions.

12. The method of claim 11, wherein each porous region is produced with a large-pored lower layer and a fine-pored upper layer.

13. The method of claim 11, wherein the wafer is heated after the porous regions have been produced, in order to produce the cover layer.

14. The method of claim 11, wherein a second semiconductor material is applied to the top side in order to produce the cover layer.

15. The method of claim 11, wherein the wafer comprises a third semiconductor material, which is arranged below the first semiconductor material, and wherein the porous regions are produced only in the first semiconductor material.

16. The method of claim 7, wherein the wafer section is freed from the second surface in the first process sequence.

17. The method of claim 7, wherein the first process sequence comprises a step of producing trenches at the top surface after the circuit structure has been produced in the defined wafer section, the trenches surrounding the defined wafer section.

18. The method of claim 17, wherein the semiconductor wafer has at least one upper, one middle and one lower material layer, wherein the circuit structure is produced in the upper material layer, and wherein the middle material layer is etched out in the first process sequence in order to free the wafer section.

19. The method of claim 18, wherein at least one passage opening is produced in the defined wafer section in order to pass an etchant to the middle material layer.