SIMD PERMUTATIONS WITH EXTENDED RANGE IN A DATA PROCESSOR

• US 20090100247A1
• Filed: 10/12/2007
• Published: 04/16/2009
• Est. Priority Date: 10/12/2007
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ahmed, Imran, Tamir, Dan E., Moyer, William C.
• Granted Patent: US 8,700,884 B2
• Time in Patent Office: Days
• US Class Current: 712/4
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

A processor in a data processing system executes a permutation instruction which identifies a first source register, at least one other source register, and a destination register. The first source register stores at least one in-range index value for the at least one other source register and at least one out-of-range index value for the at least one other source register. The at least one other source register stores a plurality of vector element values, wherein each in-range index value indicates which vector element value of the at least one other source register is to be stored into a corresponding vector element of the destination register. Each out-of-range index value is used to indicate which one of at least two predetermined constant values is to be stored into a corresponding vector element of the destination register. Partial table lookups using a permutation instruction shortens the time required to retrieve data.

Claims

1. A data processing system, comprising:

a plurality of general purpose registers; and

processor circuitry for executing one or more instructions, the one or more instructions comprising a permutation instruction which identifies a first source register from the plurality of general purpose registers, at least one other source register from the plurality of general purpose registers, and a destination register from the plurality of general purpose registers, the first source register for storing at least one in-range index value for the at least one other source register and at least one out-of-range index value for the at least one other source register, and the at least one other source register for storing a plurality of vector element values, wherein each in-range index value indicates which vector element value of the at least one other source register is to be stored into a corresponding vector element of the destination register and wherein each out-of-range index value is used to indicate which one of at least two predetermined constant values is to be stored into a corresponding vector element of the destination register.

2. The data processing system of claim 1, wherein a negative out-of-range index value indicates a first predetermined constant value of the at least two predetermined constant values to be stored into the corresponding vector element of the destination register and a positive out-of-range index value indicates a second predetermined constant value of the at least two predetermined constant values to be stored into the corresponding vector element of the destination register.

3. The data processing system of claim 2, wherein the first predetermined constant value is −

1 and the second predetermined constant value is zero.

4. The data processing system of claim 1, wherein the at least two predetermined constant values are stored in a look-up table at a location within the look-up table corresponding to the out-of-range index value.

5. The data processing system of claim 4, wherein the look-up table is a hardwired look-up table stored within the data processing system.

6. The data processing system of claim 1, wherein the first source register and the destination register are a same register of the plurality of general purpose registers.

7. The data processing system of claim 6, wherein the at least one in-range index value and the at least one out-of-range value are to be stored in a temporary location prior to storing vector element values into the destination register.

8. The data processing system of claim 1, wherein each vector element of the destination register corresponds to a vector element of first source register.

9. The data processing system of claim 1, wherein the at least one other source register comprises only one register.

10. The data processing system of claim 1, wherein the vector element values of the at least one other source register correspond to sequential values of at least a portion of a look-up table.

11. A method for performing a permutation operation, comprising:

providing a plurality of general purpose registers; and

providing processor circuitry for executing one or more instructions, the one or more instructions comprising a permutation instruction which identifies a first source register from the plurality of general purpose registers, at least one other source register from the plurality of general purpose registers, and a destination register from the plurality of general purpose registers, the first source register for storing at least one in-range index value for the at least one other source register and at least one out-of-range index value for the at least one other source register, and the at least one other source register for storing a plurality of vector element values, wherein each in-range index value indicates which vector element value of the at least one other source register is to be stored into a corresponding vector element of the destination register and wherein each out-of-range index value is used to indicate which one of at least two predetermined constant values is to be stored into a corresponding vector element of the destination register.

12. The method of claim 11, wherein a negative out-of-range index value indicates a first predetermined constant value of the at least two predetermined constant values to be stored into the corresponding vector element of the destination register and a positive out-of-range index value indicates a second predetermined constant value of the at least two predetermined constant values to be stored into the corresponding vector element of the destination register.

13. The method of claim 12, wherein the first predetermined constant value is −

1 and the second predetermined constant value is zero.

14. The method of claim 11, further comprising:

providing a look-up table, wherein the at least two predetermined constant values are stored in the look-up table at a location within the look-up table corresponding to the out-of-range index value.

15. The method of claim 11, wherein each vector element of the destination register corresponds to a vector element of first source register.

16. The method of claim 11, wherein the vector element values of the at least one other source register correspond to sequential values of a look-up table.

17. A data processing system, comprising:

a plurality of general purpose registers; and

processor circuitry for executing one or more instructions, the one or more instructions comprising a permutation instruction which identifies a first source register from the plurality of general purpose registers, at least one other source register from the plurality of general purpose registers, and a destination register from the plurality of general purpose registers, the first source register for storing at least one in-range index value for the at least one other source register, at least one positive out-of-range index value for the at least one other source register, and at least one negative out-of-range index value for the at least one other source register, and the at least one other source register for storing a plurality of vector element values, wherein each in-range index value indicates which vector element value of the at least one other source register is to be stored into a corresponding vector element of the destination register, wherein each positive out-of-range index indicates a first predetermined constant value that is to be stored into a corresponding vector element of the destination register, and wherein each negative out-of-range index indicates a second predetermined constant value to be stored into a corresponding vector element of the destination register.

18. The data processing system of claim 17, wherein the first predetermined constant value is −

1 and the second predetermined constant value is zero.

19. The data processing system of claim 17, wherein each vector element of the destination register corresponds to a vector element of first source register.

20. The data processing system of claim 17, wherein the vector element values of the at least one other source register correspond to sequential values of a look-up table.