METHOD AND APPARATUS FOR ALLOCATING ARCHITECTURAL REGISTER RESOURCES AMONG THREADS IN A MULTI-THREADED MICROPROCESSOR CORE
First Claim
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1. A microprocessor core capable of executing a plurality of threads substantially simultaneously, comprising:
- a plurality of architectural register resources available for use by the plurality of threads, where the plurality of architectural register resources is fewer in number than the plurality of threads multiplied by a number of architectural register resources required per thread;
an architecture level indicator set to correspond to the plurality of architectural register resources available for use; and
a supervisor for allocating the plurality of architectural register resources among the plurality of threads.
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Abstract
One embodiment of a microprocessor core capable of executing a plurality of threads substantially simultaneously includes a plurality of register resources available for use by the threads, where the register resources are fewer in number than the number threads multiplied by a number of architectural register resources required per thread, and a supervisor for allocating the register resources among the plurality of threads.
53 Citations
20 Claims
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1. A microprocessor core capable of executing a plurality of threads substantially simultaneously, comprising:
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a plurality of architectural register resources available for use by the plurality of threads, where the plurality of architectural register resources is fewer in number than the plurality of threads multiplied by a number of architectural register resources required per thread; an architecture level indicator set to correspond to the plurality of architectural register resources available for use; and a supervisor for allocating the plurality of architectural register resources among the plurality of threads. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for allocating a plurality of architectural register resources in a microprocessor core among a plurality of threads executing in the microprocessor core, the method comprising:
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receiving a request for a subset of the plurality of architectural register resources from a first one of the plurality of threads; de-allocating the subset of the plurality of architectural register resources from a second one of the plurality of threads, if the subset of the plurality of architectural register resources is not available; and allocating the de-allocated subset of the plurality of architectural register resources to the first one of the plurality of threads. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A computer readable medium containing an executable program for allocating a plurality of architectural register resources in a microprocessor core among a plurality of threads executing in the microprocessor core, where the program performs the steps of:
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receiving a request for a subset of the plurality of architectural register resources from a first one of the plurality of threads; de-allocating the subset of the plurality of architectural register resources from a second one of the plurality of threads, if the subset of the plurality of architectural register resources is not available; and allocating the de-allocated subset of the plurality of architectural register resources to the first one of the plurality of threads. - View Dependent Claims (14, 15, 16, 17, 18)
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19. Apparatus for allocating a plurality of architectural register resources in a microprocessor core among a plurality of threads executing in the microprocessor core, the apparatus comprising:
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means for receiving a request for a subset of the plurality of architectural register resources from a first one of the plurality of threads; means for de-allocating the subset of the plurality of architectural register resources from a second one of the plurality of threads, if the subset of the plurality of architectural register resources is not available; and means for allocating the de-allocated subset of the plurality of architectural register resources to the first one of the plurality of threads. - View Dependent Claims (20)
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Specification